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Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation

Overview of attention for book
Cover of 'Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation'

Table of Contents

  1. Altmetric Badge
    Book Overview
  2. Altmetric Badge
    Chapter 1 Connecting E-Dreams to Deep-Submicron Realities
  3. Altmetric Badge
    Chapter 2 Design Methodology for Rapid Development of SoC ICs Based on an Innovative System Architecture with Emphasis to Timing Closure and Power Consumption Optimization
  4. Altmetric Badge
    Chapter 3 Low-Voltage Embedded RAMs – Current Status and Future Trends
  5. Altmetric Badge
    Chapter 4 Adaptive Subthreshold Leakage Reduction Through N/P Wells Reverse Biasing
  6. Altmetric Badge
    Chapter 5 Leakage in CMOS Circuits – An Introduction
  7. Altmetric Badge
    Chapter 6 The Certainty of Uncertainty: Randomness in Nanometer Design
  8. Altmetric Badge
    Chapter 7 Crosstalk Cancellation for Realistic PCB Buses
  9. Altmetric Badge
    Chapter 8 A Low-Power Encoding Scheme for GigaByte Video Interfaces
  10. Altmetric Badge
    Chapter 9 Dynamic Wire Delay and Slew Metrics for Integrated Bus Structures
  11. Altmetric Badge
    Chapter 10 Perfect 3-Limited-Weight Code for Low Power I/O
  12. Altmetric Badge
    Chapter 11 A High-Level DSM Bus Model for Accurate Exploration of Transmission Behaviour and Power Estimation of Global System Buses
  13. Altmetric Badge
    Chapter 12 Performance Metric Based Optimization Protocol
  14. Altmetric Badge
    Chapter 13 Temperature Dependence in Low Power CMOS UDSM Process
  15. Altmetric Badge
    Chapter 14 Yield Optimization by Means of Process Parameters Estimation: Comparison Between ABB and ASV Techniques
  16. Altmetric Badge
    Chapter 15 High Yield Standard Cell Libraries: Optimization and Modeling
  17. Altmetric Badge
    Chapter 16 A Study of Crosstalk Through Bonding and Package Parasitics in CMOS Mixed Analog-Digital Circuits
  18. Altmetric Badge
    Chapter 17 Sleepy Stack Reduction of Leakage Power
  19. Altmetric Badge
    Chapter 18 A Cycle-Accurate Energy Estimator for CMOS Digital Circuits
  20. Altmetric Badge
    Chapter 19 Leakage Reduction at the Architectural Level and Its Application to 16 Bit Multiplier Architectures
  21. Altmetric Badge
    Chapter 20 Reducing Cross-Talk Induced Power Consumption and Delay
  22. Altmetric Badge
    Chapter 21 Investigation of Low-Power Low-Voltage Circuit Techniques for a Hybrid Full-Adder Cell
  23. Altmetric Badge
    Chapter 22 Leakage Power Analysis and Comparison of Deep Submicron Logic Gates
  24. Altmetric Badge
    Chapter 23 Threshold Mean Larger Ratio Motion Estimation in MPEG Encoding Using LNS
  25. Altmetric Badge
    Chapter 24 Energy- and Area-Efficient Deinterleaving Architecture for High-Throughput Wireless Applications
  26. Altmetric Badge
    Chapter 25 Register Isolation for Synthesizable Register Files
  27. Altmetric Badge
    Chapter 26 Discrete-Event Modeling and Simulation of Superscalar Microprocessor Architectures
  28. Altmetric Badge
    Chapter 27 Design of High-Speed Low-Power Parallel-Prefix VLSI Adders
  29. Altmetric Badge
    Chapter 28 GALSification of IEEE 802.11a Baseband Processor
  30. Altmetric Badge
    Chapter 29 TAST Profiler and Low Energy Asynchronous Design Methodology
  31. Altmetric Badge
    Chapter 30 Low Latency Synchronization Through Speculation
  32. Altmetric Badge
    Chapter 31 Minimizing the Power Consumption of an Asynchronous Multiplier
  33. Altmetric Badge
    Chapter 32 A Channel Library for Asynchronous Circuit Design Supporting Mixed-Mode Modeling
  34. Altmetric Badge
    Chapter 33 L0 Cluster Synthesis and Operation Shuffling
  35. Altmetric Badge
    Chapter 34 On Combined DVS and Processor Evaluation
  36. Altmetric Badge
    Chapter 35 A Multi-level Validation Methodology for Wireless Network Applications
  37. Altmetric Badge
    Chapter 36 SoftExplorer: Estimation, Characterization, and Optimization of the Power and Energy Consumption at the Algorithmic Level
  38. Altmetric Badge
    Chapter 37 Run-Time Software Monitor of the Power Consumption of Wireless Network Interface Cards
  39. Altmetric Badge
    Chapter 38 Towards a Software Power Cost Analysis Framework Using Colored Petri Net
  40. Altmetric Badge
    Chapter 39 A 260ps Quasi-static ALU in 90nm CMOS
  41. Altmetric Badge
    Chapter 40 Embedded EEPROM Speed Optimization Using System Power Supply Resources
  42. Altmetric Badge
    Chapter 41 Single Supply Voltage High-Speed Semi-dynamic Level-Converting Flip-Flop with Low Power and Area Consumption
  43. Altmetric Badge
    Chapter 42 A Predictive Synchronizer for Periodic Clock Domains
  44. Altmetric Badge
    Chapter 43 Power Supply Net for Adiabatic Circuits
  45. Altmetric Badge
    Chapter 44 A Novel Layout Approach Using Dual Supply Voltage Technique on Body-Tied PD-SOI
  46. Altmetric Badge
    Chapter 45 Simultaneous Wire Sizing and Decoupling Capacitance Budgeting for Robust On-Chip Power Delivery
  47. Altmetric Badge
    Chapter 46 An Efficient Low-Degree RMST Algorithm for VLSI/ULSI Physical Design
  48. Altmetric Badge
    Chapter 47 Wirelength Reduction Using 3-D Physical Design
  49. Altmetric Badge
    Chapter 48 On Skin Effect in On-Chip Interconnects
  50. Altmetric Badge
    Chapter 49 A Low and Balanced Power Implementation of the AES Security Mechanism Using Self-Timed Circuits
  51. Altmetric Badge
    Chapter 50 A Power Consumption Randomization Countermeasure for DPA-Resistant Cryptographic Processors
  52. Altmetric Badge
    Chapter 51 A Flexible and Accurate Energy Model of an Instruction-Set Simulator for Secure Smart Card Software Design
  53. Altmetric Badge
    Chapter 52 The Impact of Low-Power Techniques on the Design of Portable Safety-Critical Systems
  54. Altmetric Badge
    Chapter 53 Modular Construction and Power Modelling of Dynamic Memory Managers for Embedded Systems
  55. Altmetric Badge
    Chapter 54 PIRATE: A Framework for Power/Performance Exploration of Network-on-Chip Architectures
  56. Altmetric Badge
    Chapter 55 Power Consumption of Performance-Scaled SIMD Processors
  57. Altmetric Badge
    Chapter 56 Low Effort, High Accuracy Network-on-Chip Power Macro Modeling
  58. Altmetric Badge
    Chapter 57 Exploiting Dynamic Workload Variation in Offline Low Energy Voltage Scheduling
  59. Altmetric Badge
    Chapter 58 Design of a Power/Performance Efficient Single-Loop Sigma-Delta Modulator for Wireless Receivers
  60. Altmetric Badge
    Chapter 59 Power Aware Dividers in FPGA
  61. Altmetric Badge
    Chapter 60 A Dual Low Power and Crosstalk Immune Encoding Scheme for System-on-Chip Buses
  62. Altmetric Badge
    Chapter 61 The Effect of Data-Reuse Transformations on Multimedia Applications for Different Processing Platforms
  63. Altmetric Badge
    Chapter 62 Low Power Co-design Tool and Power Optimization of Schedules and Memory System
  64. Altmetric Badge
    Chapter 63 Hardware Building Blocks of a Mixed Granularity Reconfigurable System-on-Chip Platform
  65. Altmetric Badge
    Chapter 64 Enhancing GALS Processor Performance Using Data Classification Based on Data Latency
  66. Altmetric Badge
    Chapter 65 Application Analysis with Integrated Identification of Complex Instructions for Configurable Processors
  67. Altmetric Badge
    Chapter 66 Power Modeling, Estimation, and Optimization for Automated Co-design of Real-Time Embedded Systems
  68. Altmetric Badge
    Chapter 67 Mapping Computational Intensive Applications to a New Coarse-Grained Reconfigurable Data-Path
  69. Altmetric Badge
    Chapter 68 Power Estimation for Ripple-Carry Adders with Correlated Input Data
  70. Altmetric Badge
    Chapter 69 LPVIP: A Low-Power ROM-Less ALU for Low-Precision LNS
  71. Altmetric Badge
    Chapter 70 Low Level Adaptive Frequency in Synthesis of High Speed Digital Circuits
  72. Altmetric Badge
    Chapter 71 A Novel Mechanism for Delay-Insensitive Data Transfer Based on Current-Mode Multiple Valued Logic
  73. Altmetric Badge
    Chapter 72 Pipelines in Dynamic Dual-Rail Circuits
  74. Altmetric Badge
    Chapter 73 Optimum Buffer Size for Dynamic Voltage Processors
  75. Altmetric Badge
    Chapter 74 Design Optimization with Automated Cell Generation
  76. Altmetric Badge
    Chapter 75 A New Transistor Folding Algorithm Applied to an Automatic Full-Custom Layout Generation Tool
  77. Altmetric Badge
    Chapter 76 A Novel Constant-Time Fault-Secure Binary Counter
  78. Altmetric Badge
    Chapter 77 Buffer Sizing for Crosstalk Induced Delay Uncertainty
  79. Altmetric Badge
    Chapter 78 Optimal Logarithmic Representation in Terms of SNR Behavior
  80. Altmetric Badge
    Chapter 79 A New Logic Transformation Method for Both Low Power and High Testability
  81. Altmetric Badge
    Chapter 80 Energy-Efficient Hardware Architecture for Variable N-point 1D DCT
  82. Altmetric Badge
    Chapter 81 Two Level Compact Simulation Methodology for Timing Analysis of Power-Switched Circuits
  83. Altmetric Badge
    Chapter 82 A Generic Timing Mechanism for Using the APPLES Gate-Level Simulator in a Mixed-Level Simulation Environment
  84. Altmetric Badge
    Chapter 83 Modeling Temporal and Spatial Power Supply Voltage Variation for Timing Analysis
  85. Altmetric Badge
    Chapter 84 On Timing and Power Consumption in Inductively Coupled On-Chip Interconnects
  86. Altmetric Badge
    Chapter 85 Signal Sampling Based Transition Modeling for Digital Gates Characterization
  87. Altmetric Badge
    Chapter 86 Physical Extension of the Logical Effort Model
  88. Altmetric Badge
    Chapter 87 An Extended Transition Energy Cost Model for Buses in Deep Submicron Technologies
  89. Altmetric Badge
    Chapter 88 Moment-Based Estimation of Switching Activity for Correlated Distributions
  90. Altmetric Badge
    Chapter 89 Table-Based Total Power Consumption Estimation of Memory Arrays for Architects
  91. Altmetric Badge
    Chapter 90 A Physically Oriented Model to Quantify the Noise-on-Delay Effect
  92. Altmetric Badge
    Chapter 91 Noise Margin in Low Power SRAM Cells
  93. Altmetric Badge
    Chapter 92 Delay Evaluation of High Speed Data-Path Circuits Based on Threshold Logic
Overall attention for this book and its chapters
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About this Attention Score

  • In the top 25% of all research outputs scored by Altmetric
  • High Attention Score compared to outputs of the same age (93rd percentile)
  • High Attention Score compared to outputs of the same age and source (85th percentile)

Mentioned by

news
1 news outlet
patent
1 patent

Citations

dimensions_citation
6 Dimensions

Readers on

mendeley
2 Mendeley
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Title
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Published by
Lecture notes in computer science, January 2004
DOI 10.1007/b100662
ISBNs
978-3-54-023095-3, 978-3-54-030205-6
Authors

Khan, Zahid, Arslan, Tughrul, Erdogan, Ahmet T.

Editors

Macii, Enrico, Koufopavlou, Odysseas, Paliouras, Vassilis

View on publisher site
Mendeley readers

Mendeley readers

The data shown below were compiled from readership statistics for 2 Mendeley readers of this research output. Click here to see the associated Mendeley record.

Geographical breakdown

Country Count As %
Unknown 2 100%

Demographic breakdown

Readers by professional status Count As %
Professor > Associate Professor 1 50%
Unknown 1 50%
Readers by discipline Count As %
Engineering 1 50%
Unknown 1 50%
Attention Score in Context

Attention Score in Context

This research output has an Altmetric Attention Score of 10. This is our high-level measure of the quality and quantity of online attention that it has received. This Attention Score, as well as the ranking and number of research outputs shown below, was calculated when the research output was last mentioned on 13 September 2019.
All research outputs
#3,054,256
of 22,947,506 outputs
Outputs from Lecture notes in computer science
#637
of 8,133 outputs
Outputs of similar age
#7,972
of 133,635 outputs
Outputs of similar age from Lecture notes in computer science
#17
of 115 outputs
Altmetric has tracked 22,947,506 research outputs across all sources so far. Compared to these this one has done well and is in the 86th percentile: it's in the top 25% of all research outputs ever tracked by Altmetric.
So far Altmetric has tracked 8,133 research outputs from this source. They receive a mean Attention Score of 5.0. This one has done particularly well, scoring higher than 91% of its peers.
Older research outputs will score higher simply because they've had more time to accumulate mentions. To account for age we can compare this Altmetric Attention Score to the 133,635 tracked outputs that were published within six weeks on either side of this one in any source. This one has done particularly well, scoring higher than 93% of its contemporaries.
We're also able to compare this research output to 115 others from the same source and published within six weeks on either side of this one. This one has done well, scoring higher than 85% of its contemporaries.

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