Applied Reconfigurable Computing

Chapter 1 Improving the Performance of Adaptive Cache in Reconfigurable VLIW Processor

Chapter 2 LP-P $$^2$$ IP: A Low-Power Version of P $$^2$$ IP Architecture Using Partial Reconfiguration

Chapter 3 NIM: An HMC-Based Machine for Neuron Computation

Chapter 4 VLIW-Based FPGA Computation Fabric with Streaming Memory Hierarchy for Medical Imaging Applications

Chapter 5 Hardware Sandboxing: A Novel Defense Paradigm Against Hardware Trojans in Systems on Chip

Chapter 6 Rapid Development of Gzip with MaxJ

Chapter 7 On the Use of (Non-)Cryptographic Hashes on FPGAs

Chapter 8 An FPGA-Based Implementation of a Pipelined FFT Processor for High-Speed Signal Processing Applications

Chapter 9 Soft Timing Closure for Soft Programmable Logic Cores: The ARGen Approach

Chapter 10 FPGA Debugging with MATLAB Using a Rule-Based Inference System

Chapter 11 Hardness Analysis and Instrumentation of Verilog Gate Level Code for FPGA-based Designs

Chapter 12 A Framework for High Level Simulation and Optimization of Coarse-Grained Reconfigurable Architectures

Chapter 13 Parameter Sensitivity in Virtual FPGA Architectures

Chapter 14 Custom Framework for Run-Time Trading Strategies

Chapter 15 Exploring HLS Optimizations for Efficient Stereo Matching Hardware Implementation

Chapter 16 Architecture Reconfiguration as a Mechanism for Sustainable Performance of Embedded Systems in case of Variations in Available Power

Chapter 17 Exploring Performance Overhead Versus Soft Error Detection in Lockstep Dual-Core ARM Cortex-A9 Processor Embedded into Xilinx Zynq APSoC

Chapter 18 Applying TMR in Hardware Accelerators Generated by High-Level Synthesis Design Flow for Mitigating Multiple Bit Upsets in SRAM-Based FPGAs

Chapter 19 FPGA Applications in Unmanned Aerial Vehicles - A Review

Chapter 20 Genomic Data Clustering on FPGAs for Compression

Chapter 21 A Quantitative Analysis of the Memory Architecture of FPGA-SoCs

Chapter 22 Optimizing CNN-Based Object Detection Algorithms on Embedded FPGA Platforms

Chapter 23 An FPGA Realization of a Deep Convolutional Neural Network Using a Threshold Neuron Pruning

Chapter 24 Accuracy Evaluation of Long Short Term Memory Network Based Language Model with Fixed-Point Arithmetic

Chapter 25 FPGA Implementation of a Short Read Mapping Accelerator

Chapter 26 dfesnippets: An Open-Source Library for Dataflow Acceleration on FPGAs

Chapter 27 A Machine Learning Methodology for Cache Recommendation

Chapter 28 ArPALib: A Big Number Arithmetic Library for Hardware and Software Implementations. A Case Study for the Miller-Rabin Primality Test