Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing : 10th International Conference, FPL 2000 Villach, Austria, August 27–30, 2000 Proceedings

Table of Contents

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   Book Overview
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   Chapter 1 The Rising Wave of Field Programmability
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   Chapter 2 Tightly Integrated Design Space Exploration with Spatial and Temporal Partitioning in SPARCS
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   Chapter 3 A Dynamically Reconfigurable FPGA-Based Content Addressable Memory for Internet Protocol Characterization
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   Chapter 4 A Compiler Directed Approach to Hiding Configuration Latency in Chameleon Processors
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   Chapter 5 Reconfigurable Network Processors Based on Field Programmable System Level Integrated Circuits
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   Chapter 6 Internet Connected FPL
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   Chapter 7 Field Programmable Communication Emulation and Optimization for Embedded System Design
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   Chapter 8 FPGA-Based Emulation: Industrial and Custom Prototyping Solutions
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    Chapter 9 FPGA-Based Prototyping for Product Definition
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    Chapter 10 Implementation of Virtual Circuits by Means of the FIPSOC Devices
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    Chapter 11 Static and Dynamic Reconfigurable Designs for a 2D Shape-Adaptive DCT
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    Chapter 12 A Self-Reconfigurable Gate Array Architecture
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    Chapter 13 Multitasking on FPGA Coprocessors
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    Chapter 14 Design Visualisation for Dynamically Reconfigurable Systems
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    Chapter 15 Verification of Dynamically Reconfigurable Logic
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    Chapter 16 Design of a Fault Tolerant FPGA
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    Chapter 17 Real-Time Face Detection on a Configurable Hardware System
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    Chapter 18 Multifunctional Programmable Single-Board CAN Monitoring Module
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    Chapter 19 Self-Testing of Linear Segments in User-Programmed FPGAs
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    Chapter 20 Implementing a Fieldbus Interface Using an FPGA
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    Chapter 21 Area-Optimized Technology Mapping for Hybrid FPGAs
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    Chapter 22 CoMGen: Direct Mapping of Arbitrary Components into LUT-Based FPGAs
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    Chapter 23 Efficient Embedding of Partitioned Circuits onto Multi-FPGA Boards
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    Chapter 24 A Placement Algorithm for FPGA Designs with Multiple I/O Standards
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    Chapter 25 A Mapping Methodology for Code Trees onto LUT-Based FPGAs
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    Chapter 26 Possibilities and Limitations of Applying Evolvable Hardware to Real-World Applications
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    Chapter 27 A Co-processor System with a Virtex FPGA for Evolutionary Computation
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    Chapter 28 System Design with Genetic Algorithms
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    Chapter 29 Implementing Kak Neural Networks on a Reconfigurable Computing Platform
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    Chapter 30 Compact Spiking Neural Network Implementation in FPGA
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    Chapter 31 Silicon Platforms for the Next Generation Wireless Systems — What Role Does Reconfigurable Hardware Play?
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    Chapter 32 From Reconfigurability to Evolution in Construction Systems: Spanning the Electronic, Microfluidic and Biomolecular Domains
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    Chapter 33 A Specific Test Methodology for Symmetric SRAM-Based FPGAs
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    Chapter 34 DReAM : A Dynamica lly Reconfigura bl e Architecture for Fut ur e Mobile Communication Applications
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    Chapter 35 Fast Carrier and Phase Synchronization Units for Digital Receivers Based on Re-configurable Logic
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    Chapter 36 Software Radio Reconfigurable Hardware System (SHaRe)
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    Chapter 37 Analysis of RNS-FPL Synergy for High Throughput DSP Applications: Discrete Wavelet Transform
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    Chapter 38 Partial Run-Time Reconfiguration Using JRTR
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    Chapter 39 A Combined Approach to High-Level Synthesis for Dynamically Reconfigurable Systems
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    Chapter 40 A Hybrid Prototyping Platform for Dynamically Reconfigurable Designs
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    Chapter 41 Task Rearrangement on Partially Reconfigurable FPGAs with Restricted Buffer
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    Chapter 42 Generation of Design Suggestions for Coarse-Grain Reconfigurable Architectures
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    Chapter 43 Mapping of DSP Algorithms on Field Programmable Function Arrays
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    Chapter 44 On Availability of Bit-Narrow Operations in General-Purpose Applications
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    Chapter 45 A Comparison of FPGA Implementations of Bit-Level and Word-Level Matrix Multipliers
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    Chapter 46 A New Floorplanning Method for FPGA Architectural Research
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    Chapter 47 Efficient Self-Reconfigurable Implementations Using On-chip Memory
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    Chapter 48 Design and Implementation of an XC6216 FPGA Model in Verilog
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    Chapter 49 Reusable DSP Functions in FPGAs
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    Chapter 50 A Parallel Pipelined SAT Solver for FPGA’s
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    Chapter 51 A Multi-node Dynamic Reconfigurable Computing System with Distributed Reconfiguration Controller
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    Chapter 52 A Reconfigurable Stochastic Model Simulator for Analysis of Parallel Systems
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    Chapter 53 A CORDIC Arctangent FPGA Implementation for a High-Speed 3D-Camera System
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    Chapter 54 Reconfigurable Computing for Speech Recognition: Preliminary Findings
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    Chapter 55 Security Upgrade of Existing ISDN Devices by Using Reconfigurable Logic
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    Chapter 56 The Fastest Multiplier on FPGAs with Redundant Binary Representation
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    Chapter 57 High-Level Area and Performance Estimation of Hardware Building Blocks on FPGAs
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    Chapter 58 Balancing Logic Utilization and Area Efficiency in FPGAs
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    Chapter 59 Performance Penalty for Fault Tolerance in Roving STARs
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    Chapter 60 Optimum Functional Decomposition for LUT-Based FPGA Synthesis
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    Chapter 61 Optimization of Run-Time Reconfigurable Embedded Systems
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    Chapter 62 It’s FPL, Jim — But Not as We Know It! Opportunities for the New Commercial Architectures
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    Chapter 63 Reconfigurable Systems: New Activities in Asia
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    Chapter 64 StReAm: Object-Oriented Programming of Stream Architectures Using PAM-Blox
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    Chapter 65 Stream Computations Organized for Reconfigurable Execution (SCORE)
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    Chapter 66 Memory Access Schemes for Configurable Processors
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    Chapter 67 Generating Addresses for Multi-dimensional Array Access in FPGA On-chip Memory
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    Chapter 68 Combining Serialisation and Reconfiguration for FPGA Designs
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    Chapter 69 Multiple-Wordlength Resource Binding
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    Chapter 70 Automatic Temporal Floorplanning with Guaranteed Solution Feasibility
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    Chapter 71 A Threshold Logic-Based Reconfigurable Logic Element with a New Programming Technology
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    Chapter 72 Exploiting Reconfigurability for Effective Detection of Delay Faults in LUT-Based FPGAs
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    Chapter 73 Dataflow Partitioning and Scheduling Algorithms for WASMII, a Virtual Hardware
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    Chapter 74 Compiling Applications for ConCISe: An Example of Automatic HW/SW Partitioning and Synthesis
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    Chapter 75 Behavioural Language Compilation with Virtual Hardware Management
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    Chapter 76 Synthesis and Implementation of RAM-Based Finite State Machines in FPGAs
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    Chapter 77 Evaluation of Accelerator Designs for Subgraph Isomorphism Problem
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    Chapter 78 The Implementation of Synchronous Dataflow Graphs Using Reconfigurable Hardware
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    Chapter 79 Multiplexer Based Reconfiguration for Virtex Multipliers
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    Chapter 80 Efficient Building of Word Recognizer in FPGAs for Term-Document Matrices Construction
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    Chapter 81 Reconfigurable Computing between Classifications and Metrics — The Approach of Space/Time-Scheduling
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    Chapter 82 FPGA Implementation of a Prototype WDM On-Line Scheduler
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    Chapter 83 An FPGA Based Scheduling Coprocessor for Dynamic Priority Scheduling in Hard Real-Time Systems
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    Chapter 84 Formal Verification of a Reconfigurable Microprocessor
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    Chapter 85 The Role of the Embedded Memories in the Implementation of Artificial Neural Networks
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    Chapter 86 Programmable System Level Integration Brings System-on-Chip Design to the Desktop
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    Chapter 87 On Applying Software Development Best Practice to FPGAs in Safety-Critical Systems
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    Chapter 88 Pre-route Assistant: A Routing Tool for Run-Time Reconfiguration
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    Chapter 89 High Speed Computation of Lattice Gas Automata with FPGA
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    Chapter 90 An Implementation of Longest Prefix Matching for IP Router on Plastic Cell Architecture
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    Chapter 91 FPGA Implementation of an Extended Binary GCD Algorithm for Systolic Reduction of Rational Numbers
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    Chapter 92 Toward Uniform Approach to Design of Evolvable Hardware Based Systems
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    Chapter 93 Educational Programmable Hardware Prototyping and Verification System
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    Chapter 94 A Stream Processor Architecture Based on the Con.gurable CEPRA-S
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    Chapter 95 An Innovative Approach to Couple EDA Tools with Recon.gurable Hardware
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    Chapter 96 FPL Curriculum at Tallinn Technical University
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    Chapter 97 The Modular Architecture of SYNTHUP, FPGA Based PCI Board for Real-Time Sound Synthesis and Digital Signal Processing
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    Chapter 98 A Rapid Prototyping Environment for Microprocessor Based System-on-Chips and Its Application to the Development of a Network Processor
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     Chapter 99 Configuration Prefetching for Non-deterministic Event Driven Multi-context Schedulers
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     Chapter 100 Wireless Base Station Design Using a Reconfigurable Communications Processor
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     Chapter 101 Placement of Linear Arrays