↓ Skip to main content
What is this page? Embed badge

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation

Overview of attention for book
Cover of 'Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation'

Table of Contents

  1. Altmetric Badge
    Book Overview
  2. Altmetric Badge
    Chapter 1 Subthreshold FIR Filter Architecture for Ultra Low Power Applications
  3. Altmetric Badge
    Chapter 2 Reverse Vgs Static CMOS (RVGS-SCMOS); A New Technique for Dynamically Compensating the Process Variations in Sub-threshold Designs
  4. Altmetric Badge
    Chapter 3 Improving the Power-Delay Performance in Subthreshold Source-Coupled Logic Circuits
  5. Altmetric Badge
    Chapter 4 Design and Evaluation of Mixed 3T-4T FinFET Stacks for Leakage Reduction
  6. Altmetric Badge
    Chapter 5 Temporal Discharge Current Driven Clustering for Improved Leakage Power Reduction in Row-Based Power-Gating
  7. Altmetric Badge
    Chapter 6 Intelligate: Scalable Dynamic Invariant Learning for Power Reduction
  8. Altmetric Badge
    Chapter 7 Analysis of Effects of Input Arrival Time Variations on On-Chip Bus Power Consumption
  9. Altmetric Badge
    Chapter 8 Power-Aware Design via Micro-architectural Link to Implementation
  10. Altmetric Badge
    Chapter 9 Untraditional Approach to Computer Energy Reduction
  11. Altmetric Badge
    Chapter 10 Mixed Radix-2 and High-Radix RNS Bases for Low-Power Multiplication
  12. Altmetric Badge
    Chapter 11 Power Optimization of Parallel Multipliers in Systems with Variable Word-Length
  13. Altmetric Badge
    Chapter 12 A Design Space Comparison of 6T and 8T SRAM Core-Cells
  14. Altmetric Badge
    Chapter 13 Latched CMOS DRAM Sense Amplifier Yield Analysis and Optimization
  15. Altmetric Badge
    Chapter 14 Understanding the Effect of Intradie Random Process Variations in Nanometer Domino Logic
  16. Altmetric Badge
    Chapter 15 A Study on CMOS Time Uncertainty with Technology Scaling
  17. Altmetric Badge
    Chapter 16 Static Timing Model Extraction for Combinational Circuits
  18. Altmetric Badge
    Chapter 17 A New Bounding Technique for Handling Arbitrary Correlations in Path-Based SSTA
  19. Altmetric Badge
    Chapter 18 Statistical Modeling and Analysis of Static Leakage and Dynamic Switching Power
  20. Altmetric Badge
    Chapter 19 Logic Synthesis of Handshake Components Using Structural Clustering Techniques
  21. Altmetric Badge
    Chapter 20 Fast Universal Synchronizers
  22. Altmetric Badge
    Chapter 21 A Performance-Driven Multilevel Framework for the X-Based Full-Chip Router
  23. Altmetric Badge
    Chapter 22 PMD: A Low-Power Code for Networks-on-Chip Based on Virtual Channels
  24. Altmetric Badge
    Chapter 23 Near-Field Mapping System to Scan in Time Domain the Magnetic Emissions of Integrated Circuits
  25. Altmetric Badge
    Chapter 24 A Comparison between Two Logic Synthesis Forms from Digital Switching Noise Viewpoint
  26. Altmetric Badge
    Chapter 25 Generating Worst-Case Stimuli for Accurate Power Grid Analysis
  27. Altmetric Badge
    Chapter 26 Monolithic Multi-mode DC-DC Converter with Gate Voltage Optimization
  28. Altmetric Badge
    Chapter 27 Energy Efficiency of Power-Gating in Low-Power Clocked Storage Elements
  29. Altmetric Badge
    Chapter 28 A New Dynamic Logic Circuit Design for an Effective Trade-Off between Noise-Immunity, Performance and Energy Dissipation
  30. Altmetric Badge
    Chapter 29 Energy Efficient Elliptic Curve Processor
  31. Altmetric Badge
    Chapter 30 Energy Efficient Coarse-Grain Reconfigurable Array for Accelerating Digital Signal Processing
  32. Altmetric Badge
    Chapter 31 Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures
  33. Altmetric Badge
    Chapter 32 Settling-Optimization-Based Design Approach for Three-Stage Nested-Miller Amplifiers
  34. Altmetric Badge
    Chapter 33 Ultra Low Voltage High Speed Differential CMOS Inverter
  35. Altmetric Badge
    Chapter 34 Differential Capacitance Analysis
  36. Altmetric Badge
    Chapter 35 Automated Synchronous-to-Asynchronous Circuits Conversion: A Survey
  37. Altmetric Badge
    Chapter 36 Novel Cross-Transition Elimination Technique Improving Delay and Power Consumption for On-Chip Buses
  38. Altmetric Badge
    Chapter 37 Analytical High-Level Power Model for LUT-Based Components
  39. Altmetric Badge
    Chapter 38 A Formal Approach for Estimating Embedded System Execution Time and Energy Consumption
  40. Altmetric Badge
    Chapter 39 Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates
  41. Altmetric Badge
    Chapter 40 Disjoint Region Partitioning for Probabilistic Switching Activity Estimation at Register Transfer Level
  42. Altmetric Badge
    Chapter 41 Data Dependence of Delay Distribution for a Planar Bus
  43. Altmetric Badge
    Chapter 42 Towards Novel Approaches in Design Automation for FPGA Power Optimization
  44. Altmetric Badge
    Chapter 43 Smart Enumeration: A Systematic Approach to Exhaustive Search
  45. Altmetric Badge
    Chapter 44 An Efficient Approach for Managing Power Consumption Hotspots Distribution on 3D FPGAs
  46. Altmetric Badge
    Chapter 45 Interconnect Power Analysis for a Coarse-Grained Reconfigurable Array Processor
  47. Altmetric Badge
    Chapter 46 Integration of Power Management Units onto the SoC
  48. Altmetric Badge
    Chapter 47 Model to Hardware Matching for nm Scale Technologies
  49. Altmetric Badge
    Chapter 48 Power and Profit: Engineering in the Envelope
Overall attention for this book and its chapters
Altmetric Badge

About this Attention Score

  • Good Attention Score compared to outputs of the same age (73rd percentile)
  • Good Attention Score compared to outputs of the same age and source (70th percentile)

Mentioned by

twitter
1 X user
patent
1 patent

Citations

dimensions_citation
4 Dimensions

Readers on

mendeley
10 Mendeley
Summary X Patents Dimensions citations
You are seeing a free-to-access but limited selection of the activity Altmetric has collected about this research output. Click here to find out more.
Title
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Published by
ADS, January 2008
DOI 10.1007/978-3-540-95948-9
ISBNs
978-3-54-095947-2, 978-3-54-095948-9
Editors

Lars Svensson, José Monteiro

View on publisher site
X Demographics

X Demographics

The data shown below were collected from the profile of 1 X user who shared this research output. Click here to find out more about how the information was compiled.
 Mendeley readers

Mendeley readers

The data shown below were compiled from readership statistics for 10 Mendeley readers of this research output. Click here to see the associated Mendeley record.

Geographical breakdown

Country Count As %
Germany 2 20%
India 1 10%
Unknown 7 70%

Demographic breakdown

Readers by professional status Count As %
Student > Ph. D. Student 6 60%
Student > Bachelor 1 10%
Student > Doctoral Student 1 10%
Professor 1 10%
Professor > Associate Professor 1 10%
Other 0 0%
Readers by discipline Count As %
Computer Science 7 70%
Engineering 3 30%
Attention Score in Context

Attention Score in Context

This research output has an Altmetric Attention Score of 4. This is our high-level measure of the quality and quantity of online attention that it has received. This Attention Score, as well as the ranking and number of research outputs shown below, was calculated when the research output was last mentioned on 09 May 2017.
All research outputs
#7,282,428
of 22,977,819 outputs
Outputs from ADS
#9,052
of 37,417 outputs
Outputs of similar age
#41,091
of 156,902 outputs
Outputs of similar age from ADS
#158
of 532 outputs
Altmetric has tracked 22,977,819 research outputs across all sources so far. This one has received more attention than most of these and is in the 67th percentile.
So far Altmetric has tracked 37,417 research outputs from this source. They receive a mean Attention Score of 4.6. This one has done well, scoring higher than 75% of its peers.
Older research outputs will score higher simply because they've had more time to accumulate mentions. To account for age we can compare this Altmetric Attention Score to the 156,902 tracked outputs that were published within six weeks on either side of this one in any source. This one has gotten more attention than average, scoring higher than 73% of its contemporaries.
We're also able to compare this research output to 532 others from the same source and published within six weeks on either side of this one. This one has gotten more attention than average, scoring higher than 70% of its contemporaries.

This page is provided by Altmetric.