Languages and Compilers for Parallel Computing

Table of Contents

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   Book Overview
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   Chapter 1 Revisiting Graph Coloring Register Allocation: A Study of the Chaitin-Briggs and Callahan-Koblenz Algorithms
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   Chapter 2 Register Pressure in Software-Pipelined Loop Nests: Fast Computation and Impact on Architecture Design
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   Chapter 3 Manipulating MAXLIVE for Spill-Free Register Allocation
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   Chapter 4 Optimizing Packet Accesses for a Domain Specific Language on Network Processors
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   Chapter 5 Array Replication to Increase Parallelism in Applications Mapped to Configurable Architectures
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   Chapter 6 Generation of Control and Data Flow Graphs from Scheduled and Pipelined Assembly Code
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   Chapter 7 Applying Data Copy to Improve Memory Performance of General Array Computations
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   Chapter 8 A Cache-Conscious Profitability Model for Empirical Tuning of Loop Fusion
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    Chapter 9 Optimizing Matrix Multiplication with a Classifier Learning System
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    Chapter 10 A Language for the Compact Representation of Multiple Program Versions
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    Chapter 11 Efficient Computation of May-Happen-in-Parallel Information for Concurrent Java Programs
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    Chapter 12 Evaluating the Impact of Thread Escape Analysis on a Memory Consistency Model-Aware Compiler
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    Chapter 13 Concurrency Analysis for Parallel Programs with Textually Aligned Barriers
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    Chapter 14 Titanium Performance and Potential: An NPB Experimental Study
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    Chapter 15 Efficient Search-Space Pruning for Integrated Fusion and Tiling Transformations
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    Chapter 16 Automatic Measurement of Instruction Cache Capacity
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    Chapter 17 Combined ILP and Register Tiling: Analytical Model and Optimization Framework
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    Chapter 18 Analytic Models and Empirical Search: A Hybrid Approach to Code Optimization
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    Chapter 19 Testing Speculative Work in a Lazy/Eager Parallel Functional Language
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    Chapter 20 Loop Selection for Thread-Level Speculation
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    Chapter 21 Software Thread Level Speculation for the Java Language and Virtual Machine Environment
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    Chapter 22 Lightweight Monitoring of the Progress of Remotely Executing Computations
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    Chapter 23 Using Platform-Specific Performance Counters for Dynamic Compilation
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    Chapter 24 A Domain-Specific Interpreter for Parallelizing a Large Mixed-Language Visualisation Application
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    Chapter 25 Compiler Control Power Saving Scheme for Multi Core Processors
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    Chapter 26 Code Transformations for One-Pass Analysis
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    Chapter 27 Scalable Array SSA and Array Data Flow Analysis
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    Chapter 28 Interprocedural Symbolic Range Propagation for Optimizing Compilers
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    Chapter 29 Parallelization of Utility Programs Based on Behavior Phase Analysis
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    Chapter 30 A Systematic Approach to Model-Guided Empirical Search for Memory Hierarchy Optimization
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    Chapter 31 An Efficient Approach for Self-scheduling Parallel Loops on Multiprogrammed Parallel Computers
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    Chapter 32 Dynamic Compilation for Reducing Energy Consumption of I/O-Intensive Applications
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    Chapter 33 Supporting SELL for High-Performance Computing
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    Chapter 34 Compiler Supports and Optimizations for PAC VLIW DSP Processors