Field Programmable Logic and Application

Table of Contents

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   Book Overview
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   Chapter 1 Reconfigurable Circuits Using Hybrid Hall Effect Devices
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   Chapter 2 Gigahertz FPGA by SiGe BiCMOS Technology for Low Power, High Speed Computing with 3-D Memory
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   Chapter 3 Implementing an OFDM Receiver on the RaPiD Reconfigurable Architecture
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   Chapter 4 Symbol Timing Synchronization in FPGA-Based Software Radios: Application to DVB-S
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   Chapter 5 An Algorithm Designer’s Workbench for Platform FPGAs
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   Chapter 6 Prototyping for the Concurrent Development of an IEEE 802.11 Wireless LAN Chipset
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   Chapter 7 ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix
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   Chapter 8 Inter-processor Connection Reconfiguration Based on Dynamic Look-Ahead Control of Multiple Crossbar Switches
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    Chapter 9 Arbitrating Instructions in an ρμ -Coded CCM
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    Chapter 10 How Secure Are FPGAs in Cryptographic Applications?
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    Chapter 11 FPGA Implementations of the RC6 Block Cipher
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    Chapter 12 Very High Speed 17 Gbps SHACAL Encryption Architecture
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    Chapter 13 Track Placement: Orchestrating Routing Structures to Maximize Routability
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    Chapter 14 Quark Routing
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    Chapter 15 Global Routing for Lookup-Table Based FPGAs Using Genetic Algorithms
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    Chapter 16 Virtualizing Hardware with Multi-context Reconfigurable Arrays
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    Chapter 17 A Dynamically Adaptive Switching Fabric on a Multicontext Reconfigurable Device
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    Chapter 18 Reducing the Configuration Loading Time of a Coarse Grain Multicontext Reconfigurable Device
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    Chapter 19 Design Strategies and Modified Descriptions to Optimize Cipher FPGA Implementations: Fast and Compact Results for DES and Triple-DES
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    Chapter 20 Using Partial Reconfiguration in Cryptographic Applications: An Implementation of the IDEA Algorithm
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    Chapter 21 An Implementation Comparison of an IDEA Encryption Cryptosystem on Two General-Purpose Reconfigurable Computers
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    Chapter 22 Data Processing System with Self-reconfigurable Architecture, for Low Cost, Low Power Applications
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    Chapter 23 Low Power Coarse-Grained Reconfigurable Instruction Set Processor
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    Chapter 24 Encoded-Low Swing Technique for Ultra Low Power Interconnect
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    Chapter 25 Building Run-Time Reconfigurable Systems from Tiles
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    Chapter 26 Exploiting Redundancy to Speedup Reconfiguration of an FPGA
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    Chapter 27 Run-Time Exchange of Mechatronic Controllers Using Partial Hardware Reconfiguration
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    Chapter 28 Efficient Modular-Pipelined AES Implementation in Counter Mode on ALTERA FPGA
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    Chapter 29 An FPGA-Based Performance Analysis of the Unrolling, Tiling, and Pipelining of the AES Algorithm
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    Chapter 30 Two Approaches for a Single-Chip FPGA Implementation of an Encryptor/Decryptor AES Core
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    Chapter 31 Performance and Area Modeling of Complete FPGA Designs in the Presence of Loop Transformations
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    Chapter 32 Branch Optimisation Techniques for Hardware Compilation
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    Chapter 33 A Model for Hardware Realization of Kernel Loops
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    Chapter 34 Programmable Asynchronous Pipeline Arrays
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    Chapter 35 Globally Asynchronous Locally Synchronous FPGA Architectures
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    Chapter 36 Case Study of a Functional Genomics Application for an FPGA-Based Coprocessor
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    Chapter 37 A Smith-Waterman Systolic Cell
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    Chapter 38 Software Decelerators
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    Chapter 39 A Unified Codesign Run-Time Environment for the UltraSONIC Reconfigurable Computer
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    Chapter 40 Extra-dimensional Island-Style FPGAs
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    Chapter 41 Using Multiplexers for Control and Data in D-Fabrix
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    Chapter 42 Heterogeneous Logic Block Architectures for Via-Patterned Programmable Fabrics
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    Chapter 43 A Real-Time Visualization System for PIV
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    Chapter 44 A Real-Time Stereo Vision System with FPGA
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    Chapter 45 Synthesizing on a Reconfigurable Chip an Autonomous Robot Image Processing System
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    Chapter 46 Reconfigurable Hardware SAT Solvers: A Survey of Systems
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    Chapter 47 Fault Tolerance Analysis of Distributed Reconfigurable Systems Using SAT-Based Techniques
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    Chapter 48 Hardware Implementations of Real-Time Reconfigurable WSAT Variants
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    Chapter 49 Core-Based Reusable Architecture for Slave Circuits with Extensive Data Exchange Requirements
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    Chapter 50 Time and Energy Efficient Matrix Factorization Using FPGAs
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    Chapter 51 Improving DSP Performance with a Small Amount of Field Programmable Logic
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    Chapter 52 Fully Parameterized Discrete Wavelet Packet Transform Architecture Oriented to FPGA
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    Chapter 53 An FPGA System for the High Speed Extraction, Normalization and Classification of Moment Descriptors
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    Chapter 54 Design and Implementation of a Novel FIR Filter Architecture with Boundary Handling on Xilinx VIRTEX FPGAs
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    Chapter 55 A Self-reconfiguring Platform
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    Chapter 56 Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices
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    Chapter 57 Run-Time Minimization of Reconfiguration Overhead in Dynamically Reconfigurable Systems
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    Chapter 58 Networks on Chip as Hardware Components of an OS for Reconfigurable Systems
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    Chapter 59 A Reconfigurable Platform for Real-Time Embedded Video Image Processing
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    Chapter 60 Emulation-Based Analysis of Soft Errors in Deep Sub-micron Circuits
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    Chapter 61 HW-Driven Emulation with Automatic Interface Generation
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    Chapter 62 Implementation of HW$im – A Real-Time Configurable Cache Simulator
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    Chapter 63 The Bank Nth Chance Replacement Policy for FPGA-Based CAMs
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    Chapter 64 Variable Precision Multipliers for FPGA-Based Reconfigurable Computing Systems
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    Chapter 65 A New Arithmetic Unit in GF(2 m ) for Reconfigurable Hardware Implementation
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    Chapter 66 A Dynamic Routing Algorithm for a Bio-inspired Reconfigurable Circuit
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    Chapter 67 An FPL Bioinspired Visual Encoding System to Stimulate Cortical Neurons in Real-Time
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    Chapter 68 Power Analysis of FPGAs: How Practical Is the Attack?
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    Chapter 69 A Power-Scalable Motion Estimation Architecture for Energy Constrained Applications
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    Chapter 70 A Novel Approach for Architectural Models Characterization. An Example through the Systolic Ring
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    Chapter 71 A Generic Architecture for Integrated Smart Transducers
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    Chapter 72 Customisable Core-Based Architectures for Real-Time Motion Estimation on FPGAs
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    Chapter 73 A High Speed Computation System for 3D FCHC Lattice Gas Model with FPGA
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    Chapter 74 Implementation of ReCSiP: A ReConfigurable Cell SImulation Platform
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    Chapter 75 On the Implementation of a Margolus Neighborhood Cellular Automata on FPGA
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    Chapter 76 Fast Modular Division for Application in ECC on Reconfigurable Logic
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    Chapter 77 Non-uniform Segmentation for Hardware Function Evaluation
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    Chapter 78 A Dual-Path Logarithmic Number System Addition/Subtraction Scheme for FPGA
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    Chapter 79 A Modular Reconfigurable Architecture for Efficient Fault Simulation in Digital Circuits
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    Chapter 80 Evaluation of Testability of Path Delay Faults for User-Configured Programmable Devices
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    Chapter 81 Fault Simulation Using Partially Reconfigurable Hardware
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    Chapter 82 Switch Level Fault Emulation
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    Chapter 83 An Extensible, System-On-Programmable-Chip, Content-Aware Internet Firewall
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    Chapter 84 IPsec-Protected Transport of HDTV over IP
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    Chapter 85 Fast, Large-Scale String Match for a 10Gbps FPGA-Based Network Intrusion Detection System
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    Chapter 86 Irregular Reconfigurable CAM Structures for Firewall Applications
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    Chapter 87 Compiling for the Molen Programming Paradigm
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    Chapter 88 Laura: Leiden Architecture Research and Exploration Tool
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    Chapter 89 Communication Costs Driven Design Space Exploration for Reconfigurable Architectures
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    Chapter 90 From Algorithm Graph Specification to Automatic Synthesis of FPGA Circuit: A Seamless Flow of Graphs Transformations
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    Chapter 91 Adaptive Real-Time Systems and the FPAA
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    Chapter 92 Challenges and Successes in Space Based Reconfigurable Computing
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    Chapter 93 Adaptive Processor: A Dynamically Reconfiguration Technology for Stream Processing
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    Chapter 94 Efficient Reconfigurable Logic Circuits for Matching Complex Network Intrusion Detection Patterns
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    Chapter 95 FPGAs for High Accuracy Clock Synchronization over Ethernet Networks
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    Chapter 96 Project of IPv6 Router with FPGA Hardware Accelerator
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    Chapter 97 A TCP/IP Based Multi-device Programming Circuit
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    Chapter 98 Design Flow for Efficient FPGA Reconfiguration
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     Chapter 99 High-Level Design Tools for FPGA-Based Combinatorial Accelerators
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     Chapter 100 Field Programmable Logic and Application
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     Chapter 101 MATLAB/Simulink Based Methodology for Rapid-FPGA-Prototyping
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     Chapter 102 DIGIMOD: A Tool to Implement FPGA-Based Digital IF and Baseband Modems
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     Chapter 103 FPGA Implementation of a Maze Routing Accelerator
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     Chapter 104 Model Checking Reconfigurable Processor Configurations for Safety Properties
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     Chapter 105 A Statistical Analysis Tool for FPLD Architectures
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     Chapter 106 FPGA-Implementation of Signal Processing Algorithms for Video Based Industrial Safety Applications
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     Chapter 107 Configurable Hardware Architecture for Real-Time Window-Based Image Processing
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     Chapter 108 An FPGA-Based Image Connected Component Labeller
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     Chapter 109 FPGA Implementation of Adaptive Non-linear Predictors for Video Compression
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     Chapter 110 Reconfigurable Systems in Education
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     Chapter 111 Data Dependent Circuit Design: A Case Study
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     Chapter 112 Design of a Power Conscious, Customizable CDMA Receiver
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     Chapter 113 Power-Efficient Implementations of Multimedia Applications on Reconfigurable Platforms
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     Chapter 114 A VHDL Library to Analyse Fault Tolerant Techniques
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     Chapter 115 Hardware Design with a Scripting Language
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     Chapter 116 Testable Clock Routing Architecture for Field Programmable Gate Arrays
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     Chapter 117 FPGA Implementation of Multi-layer Perceptrons for Speech Recognition
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     Chapter 118 FPGA Based High Density Spiking Neural Network Array
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     Chapter 119 FPGA-Based Computation of Free-Form Deformations
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     Chapter 120 FPGA Implementations of Neural Networks – A Survey of a Decade of Progress
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     Chapter 121 FPGA-Based Hardware/Software CoDesign of an Expert System Shell
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     Chapter 122 Cluster-Driven Hardware/Software Partitioning and Scheduling Approach for a Reconfigurable Computer System
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     Chapter 123 Hardware-Software Codesign in Embedded Asymmetric Cryptography Application – A Case Study
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     Chapter 124 On-chip and Off-chip Real-Time Debugging for Remotely-Accessed Embedded Programmable Systems
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     Chapter 125 Fast Region Labeling on the Reconfigurable Platform ACE-V
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     Chapter 126 Modified Fuzzy C-Means Clustering Algorithm for Real-Time Applications
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     Chapter 127 Reconfigurable Hybrid Architecture for Web Applications
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     Chapter 128 FPGA Implementation of the Adaptive Lattice Filter
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     Chapter 129 Specifying Control Logic for DSP Applications in FPGAs
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     Chapter 130 FPGA Processor for Real-Time Optical Flow Computation
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     Chapter 131 A Data Acquisition Reconfigurable Coprocessor for Virtual Instrumentation Applications
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     Chapter 132 Evaluation and Run-Time Optimization of On-chip Communication Structures in Reconfigurable Architectures
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     Chapter 133 A Controlled Data-Path Allocation Model for Dynamic Run-Time Reconfiguration of FPGA Devices
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     Chapter 134 Architecture Template and Design Flow to Support Application Parallelism on Reconfigurable Platforms
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     Chapter 135 Efficient Implementation of the Singular Value Decomposition on a Reconfigurable System
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     Chapter 136 A New Reconfigurable-Oriented Method for Canonical Basis Multiplication over a Class of Finite Fields GF(2 m )
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     Chapter 137 A Study on the Design of Floating-Point Functions in FPGAs
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     Chapter 138 Design and Implementation of RNS-Based Adaptive Filters
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     Chapter 139 Domain-Specific Reconfigurable Array for Distributed Arithmetic
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     Chapter 140 Design and Implementation of Priority Queuing Mechanism on FPGA Using Concurrent Periodic EFSMs and Parametric Model Checking
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     Chapter 141 Custom Tag Computation Circuit for a 10Gbps SCFQ Scheduler
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     Chapter 142 Exploiting Stateful Inspection of Network Security in Reconfigurable Hardware
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     Chapter 143 Propose of a Hardware Implementation for Fingerprint Systems
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     Chapter 144 APPLES: A Full Gate-Timing FPGA-Based Hardware Simulator
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     Chapter 145 Designing, Scheduling, and Allocating Flexible Arithmetic Components
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     Chapter 146 UNSHADES-1: An Advanced Tool for In-System Run-Time Hardware Debugging