Correct Hardware Design and Verification Methods

Table of Contents

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   Book Overview
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   Chapter 1 Esterel and Jazz : Two Synchronous Languages for Circuit Design
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   Chapter 2 Design Process of Embedded Automotive Systems—Using Model Checking for Correct Specifications
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   Chapter 3 A Proof of Correctness of a Processor Implementing Tomasulo’s Algorithm without a Reorder Buffer
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   Chapter 4 Formal Verification of Explicitly Parallel Microprocessors
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   Chapter 5 Superscalar Processor Verification Using Efficient Reductions of the Logic of Equality with Uninterpreted Functions to Propositional Logic
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   Chapter 6 Model Checking TLA+ Specifications
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   Chapter 7 Efficient Decompositional Model Checking for Regular Timing Diagrams
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   Chapter 8 Vacuity Detection in Temporal Model Checking
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    Chapter 9 Using Symbolic Model Checking to Verify the Railway Stations of Hoorn-Kersenboogerd and Heerhugowaard
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    Chapter 10 Practical Application of Formal Verification Techniques on a Frame Mux/Demux Chip from Nortel Semiconductors
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    Chapter 11 Efficient Verification of Timed Automata Using Dense and Discrete Time Semantics
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    Chapter 12 From Asymmetry to Full Symmetry: New Techniques for Symmetry Reduction in Model Checking
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    Chapter 13 Automatic Error Correction of Large Circuits Using Boolean Decomposition and Abstraction
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    Chapter 14 Abstract BDDs: A Technique for Using Abstraction in Model Checking
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    Chapter 15 Formal Synthesis at the Algorithmic Level
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    Chapter 16 Xs Are for Trajectory Evaluation, Booleans Are for Theorem Proving
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    Chapter 17 Verification of Infinite State Systems by Compositional Model Checking
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    Chapter 18 Formal Verification of Designs with Complex Control by Symbolic Simulation
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    Chapter 19 Hints to Accelerate Symbolic Traversal
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    Chapter 20 Modeling and Checking Networks of Communicating Real-Time Processes
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    Chapter 21 ”Have I Written Enough Properties?” - A Method of Comparison Between Specification and Implementation
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    Chapter 22 Program Slicing of Hardware Description Languages
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    Chapter 23 Results of the Verification of a Complex Pipelined Machine Model
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    Chapter 24 Hazard—Freedom Checking in Speed—Independent Systems
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    Chapter 25 Yet Another Look at LTL Model Checking
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    Chapter 26 Verification of Finite-State-Machine Refinements Using a Symbolic Methodology
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    Chapter 27 Refinement and Property Checking in High-Level Synthesis Using Attribute Grammars
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    Chapter 28 A Systematic Incrementalization Technique and Its Application to Hardware Design
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    Chapter 29 Bisimulation and Model Checking
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    Chapter 30 Circular Compositional Reasoning about Liveness
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    Chapter 31 Symbolic Simulation of Microprocessor Models Using Type Classes in Haskell
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    Chapter 32 Exploiting Retiming in a Guided Simulation Based Validation Methodology
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    Chapter 33 Fault Models for Embedded Systems
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    Chapter 34 Validation of Object-Oriented Concurrent Designs by Model Checking