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Software and Compilers for Embedded Systems

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Cover of 'Software and Compilers for Embedded Systems'

Table of Contents

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    Book Overview
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    Chapter 1 The Transmeta Crusoe: VLIW Embedded in CISC
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    Chapter 2 Limited Address Range Architecture for Reducing Code Size in Embedded Processors
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    Chapter 3 Predicated Instructions for Code Compaction
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    Chapter 4 Code Generation for a Dual Instruction Set Processor Based on Selective Code Transformation
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    Chapter 5 Code Instruction Selection Based on SSA-Graphs
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    Chapter 6 A Code Selection Method for SIMD Processors with PACK Instructions
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    Chapter 7 Reconstructing Control Flow from Predicated Assembly Code
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    Chapter 8 Control Flow Analysis for Recursion Removal
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    Chapter 9 An Unfolding-Based Loop Optimization Technique
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    Chapter 10 Tailoring Software Pipelining for Effective Exploitation of Zero Overhead Loop Buffer
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    Chapter 11 Case Studies on Automatic Extraction of Target-Specific Architectural Parameters in Complex Code Generation
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    Chapter 12 Extraction of Efficient Instruction Schedulers from Cycle-True Processor Models
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    Chapter 13 A Framework for the Design and Validation of Efficient Fail-Safe Fault-Tolerant Programs
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    Chapter 14 A Case Study on a Component-Based System and Its Configuration
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    Chapter 15 Composable Code Generation for Model-Based Development
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    Chapter 16 Code Generation for Packet Header Intrusion Analysis on the IXP1200 Network Processor
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    Chapter 17 Retargetable Graph-Coloring Register Allocation for Irregular Architectures
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    Chapter 18 Fine-Grain Register Allocation Based on a Global Spill Costs Analysis
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    Chapter 19 Unified Instruction Reordering and Algebraic Transformations for Minimum Cost Offset Assignment
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    Chapter 20 Improving Offset Assignment through Simultaneous Variable Coalescing
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    Chapter 21 Transformation of Meta-Information by Abstract Co-interpretation
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    Chapter 22 Performance Analysis for Identification of (Sub-)Task-Level Parallelism in Java
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    Chapter 23 Towards Superinstructions for Java Interpreters
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    Chapter 24 Partitioning for DSP Software Synthesis
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    Chapter 25 Efficient Variable Allocation to Dual Memory Banks of DSPs
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    Chapter 26 Cache Behavior Modeling of Codes with Data-Dependent Conditionals
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    Chapter 27 FICO: A Fast Instruction Cache Optimizer
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Title
Software and Compilers for Embedded Systems
Published by
Springer Berlin Heidelberg, October 2003
DOI 10.1007/b13482
ISBNs
978-3-54-020145-8, 978-3-54-039920-9
Editors

Krall, Andreas

Mendeley readers

Mendeley readers

The data shown below were compiled from readership statistics for 2 Mendeley readers of this research output. Click here to see the associated Mendeley record.

Geographical breakdown

Country Count As %
Unknown 2 100%

Demographic breakdown

Readers by professional status Count As %
Student > Bachelor 1 50%
Student > Ph. D. Student 1 50%
Readers by discipline Count As %
Business, Management and Accounting 1 50%
Engineering 1 50%