Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation

Table of Contents

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   Book Overview
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   Chapter 1 Architectural Challenges for the Next Decade Integrated Platforms
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   Chapter 2 Analysis of High-Speed Logic Families
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   Chapter 3 Low Voltage, Double-Edge-Triggered Flip Flop
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   Chapter 4 A Genetic Bus Encoding Technique for Power Optimization of Embedded Systems
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   Chapter 5 State Encoding for Low-Power FSMs in FPGA
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   Chapter 6 Reduced Leverage of Dual Supply Voltages in Ultra Deep Submicron Technologies
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   Chapter 7 A Compact Charge-Based Crosstalk Induced Delay Model for Submicronic CMOS Gates
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   Chapter 8 CMOS Gate Sizing under Delay Constraint
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    Chapter 9 Process Characterisation for Low VTH and Low Power Design
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    Chapter 10 Power and Energy Consumption of CMOS Circuits: Measurement Methods and Experimental Results
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    Chapter 11 Effects of Temperature in Deep-Submicron Global Interconnect Optimization
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    Chapter 12 Interconnect Parasitic Extraction Tool for Radio-Frequency Integrated Circuits
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    Chapter 13 Estimation of Crosstalk Noise for On-Chip Buses
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    Chapter 14 A Block-Based Approach for SoC Global Interconnect Electrical Parameters Characterization
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    Chapter 15 Interconnect Driven Low Power High-Level Synthesis
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    Chapter 16 Bridging Clock Domains by Synchronizing the Mice in the Mousetrap
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    Chapter 17 Power-Consumption Reduction in Asynchronous Circuits Using Delay Path Unequalization
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    Chapter 18 New GALS Technique for Datapath Architectures
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    Chapter 19 Power/Area Tradeoffs in 1-of-M Parallel-Prefix Asynchronous Adders
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    Chapter 20 Static Implementation of QDI Asynchronous Primitives
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    Chapter 21 The Emergence of Design for Energy Efficiency: An EDA Perspective
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    Chapter 22 The Most Complete Mixed-Signal Simulation Solution with ADVance MS
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    Chapter 23 Signal Integrity and Power Supply Network Analysis of Deep SubMicron Chips
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    Chapter 24 Power Management in Synopsys Galaxy Design Platform
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    Chapter 25 Open Multimedia Platform for Next-Generation Mobile Devices
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    Chapter 26 Statistical Power Estimation of Behavioral Descriptions
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    Chapter 27 A Statistical Power Model for Non-synthetic RTL Operators
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    Chapter 28 Energy Efficient Register Renaming
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    Chapter 29 Stand-by Power Reduction for Storage Circuits
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    Chapter 30 A Unified Framework for Power-Aware Design of Embedded Systems
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    Chapter 31 A Flexible Framework for Fast Multi-objective Design Space Exploration of Embedded Systems
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    Chapter 32 High-Level Area and Current Estimation
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    Chapter 33 Switching Activity Estimation in Non-linear Architectures
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    Chapter 34 Instruction Level Energy Modeling for Pipelined Processors
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    Chapter 35 Power Estimation Approach of Dynamic Data Storage on a Hardware Software Boundary Level
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    Chapter 36 An Adiabatic Charge Pump Based Charge Recycling Design Style
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    Chapter 37 Reduction of the Energy Consumption in Adiabatic Gates by Optimal Transistor Sizing
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    Chapter 38 Low-Power Response Time Accelerator with Full Resolution for LCD Panel
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    Chapter 39 Memory Compaction and Power Optimization for Wavelet-Based Coders
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    Chapter 40 Design Space Exploration and Trade-Offs in Analog Amplifier Design
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    Chapter 41 Power and Timing Driven Physical Design Automation
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    Chapter 42 Analysis of Energy Consumed by Secure Session Negotiation Protocols in Wireless Networks
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    Chapter 43 Remote Power Control of Wireless Network Interfaces
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    Chapter 44 Architecture-Driven Voltage Scaling for High-Throughput Turbo-Decoders
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    Chapter 45 A Fully Digital Numerical-Controlled-Oscillator
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    Chapter 46 Energy Optimization of High-Performance Circuits
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    Chapter 47 Instruction Buffering Exploration for Low Energy Embedded Processors
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    Chapter 48 Power-Aware Branch Predictor Update for High-Performance Processors
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    Chapter 49 Power Optimization Methodology for Multimedia Applications Implementation on Reconfigurable Platforms
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    Chapter 50 High-Level Algorithmic Complexity Analysis for the Implementation of a Motion-JPEG2000 Encoder
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    Chapter 51 Metric Definition for Circuit Speed Optimization
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    Chapter 52 Optical versus Electrical Interconnections for Clock Distribution Networks in New VLSI Technologies
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    Chapter 53 An Asynchronous Viterbi Decoder for Low-Power Applications
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    Chapter 54 Analysis of the Contribution of Interconnect Effects in Energy Dissipation of VLSI Circuits
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    Chapter 55 A New Hybrid CBL-CMOS Cell for Optimum Noise/Power Application
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    Chapter 56 Computational Delay Models to Estimate the Delay of Floating Cubes in CMOS Circuits
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    Chapter 57 A Practical ASIC Methodology for Flexible Clock Tree Synthesis with Routing Blockages
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    Chapter 58 Frequent Value Cache for Low-Power Asynchronous Dual-Rail Bus
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    Chapter 59 Reducing Static Energy of Cache Memories via Prediction-Table-Less Way Prediction
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    Chapter 60 A Bottom-Up Approach to On-Chip Signal Integrity
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    Chapter 61 Advanced Cell Modeling Techniques Based on Polynomial Expressions
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    Chapter 62 RTL-Based Signal Statistics Calculation Facilitates Low Power Design Approaches
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    Chapter 63 Data Dependences Critical Path Evaluation at C/C++ System Level Description
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    Chapter 64 A Hardware/Software Partitioning and Scheduling Approach for Embedded Systems with Low-Power and High Performance Requirements
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    Chapter 65 Consideration of Control System and Memory Contributions in Practical Resource-Constrained Scheduling for Low Power
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    Chapter 66 Low-Power Cache with Successive Tag Comparison Algorithm
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    Chapter 67 FPGA Architecture Design and Toolset for Logic Implementation
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    Chapter 68 Bit-Level Allocation for Low Power in Behavioural High-Level Synthesis