VLSI Design and Test

Table of Contents

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   Book Overview
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   Chapter 1 Flexible Composite Galois Field $$GF((2^m)^2)$$ Multiplier Designs
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   Chapter 2 Estimating the Maximum Propagation Delay of 4-bit Ripple Carry Adder Using Reduced Input Transitions
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   Chapter 3 VLSI Implementation of Throughput Efficient Distributed Arithmetic Based LMS Adaptive Filter
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   Chapter 4 Realization of Multiplier Using Delay Efficient Cyclic Redundant Adder
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   Chapter 5 Fast Architecture of Modular Inversion Using Itoh-Tsujii Algorithm
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   Chapter 6 Performance Optimized 64b/66b Line Encoding Technique for High Speed SERDES Devices
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   Chapter 7 A New Multi-objective Hardware-Software-Partitioning Algorithmic Approach for High Speed Applications
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   Chapter 8 A Framework for Branch Predictor Selection with Aggregation on Multiple Parameters
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    Chapter 9 FPGA Implementation of a Novel Area Efficient FFT Scheme Using Mixed Radix FFT
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    Chapter 10 Low Voltage, Low Power Transconductor for Low Frequency $$G_m$$ -C Filters
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    Chapter 11 An Improved Highly Efficient Low Input Voltage Charge Pump Circuit
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    Chapter 12 A Calibration Technique for Current Steering DACs - Self Calibration with Capacitor Storage
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    Chapter 13 Characterization and Compensation Circuitry for Piezo-Resistive Pressure Sensor to Accommodate Temperature Induced Variation
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    Chapter 14 FEM Based Device Simulator for High Voltage Devices
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    Chapter 15 Synapse Circuits Implementation and Analysis in 180 nm MOSFET and CNFET Technology
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    Chapter 16 A 10 MHz, 73 ppm/°C, 84 µW PVT Compensated Ring Oscillator
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    Chapter 17 Deterministic Shift Power Reduction in Test Compression
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    Chapter 18 Pseudo-BIST: A Novel Technique for SAR-ADC Testing
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    Chapter 19 SFG Based Fault Simulation of Linear Analog Circuits Using Fault Classification and Sensitivity Analysis
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    Chapter 20 A Cost Effective Technique for Diagnosis of Scan Chain Faults
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    Chapter 21 Multi-mode Toggle Random Access Scan to Minimize Test Application Time
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    Chapter 22 Performance Analysis of Disability Based Fault Tolerance Techniques for Permanent Faults in Chip Multiprocessors
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    Chapter 23 Low-Power Sequential Circuit Design Using Work-Function Engineered FinFETs
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    Chapter 24 Vertical Nanowire FET Based Standard Cell Design Employing Verilog-A Compact Model for Higher Performance
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    Chapter 25 Analysis of Electrolyte-Insulator-Semiconductor Tunnel Field-Effect Transistor as pH Sensor
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    Chapter 26 Exploiting Characteristics of Steep Slope Tunnel Transistors Towards Energy Efficient and Reliable Buffer Designs for IoT SoCs
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    Chapter 27 An Efficient VLSI Architecture for PRESENT Block Cipher and Its FPGA Implementation
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    Chapter 28 Investigation of TCADs Models for Characterization of Sub 16 nm In $$_{0.53}$$ Ga $$_{0.47}$$ As FinFET
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    Chapter 29 Hausdorff Distance Driven L-Shape Matching Based Layout Decomposition for E-Beam Lithography
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    Chapter 30 Energy-Efficient VLSI Architecture & Implementation of Bi-modal Multi-banked Register-File Organization
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    Chapter 31 Performance-Enhanced $$d^2$$ -LBDR for 2D Mesh Network-on-Chip
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    Chapter 32 ACAM: Application Aware Adaptive Cache Management for Shared LLC
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    Chapter 33 Adaptive Packet Throttling Technique for Congestion Management in Mesh NoCs
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    Chapter 34 Defeating HaTCh: Building Malicious IP Cores
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    Chapter 35 Low Cost Circuit Level Implementation of PRESENT-80 S-BOX
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    Chapter 36 Modeling and Analysis of Transient Heat for 3D IC
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    Chapter 37 Memory Efficient Fractal-SPIHT Based Hybrid Image Encoder
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    Chapter 38 Metal-Oxide Nanostructures Designed by Glancing Angle Deposition Technique and Its Applications on Sensors and Optoelectronic Devices: A Review
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    Chapter 39 Low Write Energy STT-MRAM Cell Using 2T- Hybrid Tunnel FETs Exploiting the Steep Slope and Ambipolar Characteristics
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    Chapter 40 Enhancing Retention Voltage for SRAM
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    Chapter 41 Comparison of SRAM Cell Layout Topologies to Estimate Improvement in SER Robustness in 28FDSOI and 40 nm Technologies
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    Chapter 42 Improving the Design of Nearest Neighbor Quantum Circuits in 2D Space
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    Chapter 43 Delay and Frequency Investigations in Coupled MLGNR Interconnects
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    Chapter 44 LISOCHIN: An NBTI Degradation Monitoring Sensor for Reliable CMOS Circuits
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    Chapter 45 Performance Analysis of OLED with Hole Block Layer and Impact of Multiple Hole Block Layer
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    Chapter 46 Improved Gate Modulation in Tunnel Field Effect Transistors with Non-rectangular Tapered Y-Gate Geometry
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    Chapter 47 A 36 nW Power Management Unit for Solar Energy Harvesters Using 0.18  $$\upmu $$ m CMOS
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    Chapter 48 A 10T Subthreshold SRAM Cell with Minimal Bitline Switching for Ultra-Low Power Applications
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    Chapter 49 Variability Investigation of Double Gate JunctionLess (DG-JL) Transistor for Circuit Design Perspective
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    Chapter 50 A High Speed KECCAK Coprocessor for Partitioned NSP Architecture on FPGA Platform
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    Chapter 51 New Energy Efficient Reconfigurable FIR Filter Architecture and Its VLSI Implementation
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    Chapter 52 FPGA-Based Smart Camera System for Real-Time Automated Video Surveillance
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    Chapter 53 Effectiveness of High Permittivity Spacer for Underlap Regions of Wavy-Junctionless FinFET at 22 nm Node and Scaling Short Channel Effects
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    Chapter 54 Design and Implementation of Ternary Content Addressable Memory (TCAM) Based Hierarchical Motion Estimation for Video Processing
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    Chapter 55 A Custom Designed RISC-V ISA Compatible Processor for SoC
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    Chapter 56 An Efficient Timing and Clock Tree Aware Placement Flow with Multibit Flip-Flops for Power Reduction
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    Chapter 57 Primitive Instantiation Based Fault Localization Circuitry for High Performance FPGA Designs
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    Chapter 58 On Generation of Delay Test with Capture Power Safety
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    Chapter 59 A Configurable and Area Efficient Technique for Implementing Isolation Cells in Low Power SoC
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    Chapter 60 A 10 MHz, 42 ppm/ $$ ^{ \circ } {\text{C}} $$ , 69 μW PVT Compensated Latch Based Oscillator in BCD9S Technology for PCM
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    Chapter 61 A 1.8 V Gain Enhanced Fully Differential Doubly-Recycled Cascode OTA with 100 dB Gain 200 MHz UGB in CMOS
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    Chapter 62 A Low Power, Frequency-to-Digital Converter CMOS Based Temperature Sensor in 65 nm Process
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    Chapter 63 Design & Development of High Speed LVDS Receiver with Cold-Spare Feature in SCL’s 0.18 µm CMOS Process
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    Chapter 64 Fast FPGA Placement Using Analytical Optimization
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    Chapter 65 A Dependability Preserving Fluid-Level Synthesis for Reconfigurable Droplet-Based Microfluidic Biochips
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    Chapter 66 Splitting and Transport of a Droplet with No External Actuation Force for Lab on Chip Devices
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    Chapter 67 Analytical Partitioning: Improvement over FM
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    Chapter 68 A Lifting Instruction for Performing DWT in LEON3 Processor Based System-on-Chip
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    Chapter 69 Droplet Position Estimator for Open EWOD System Using Open Source Computer Vision
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    Chapter 70 Design and Implementation of Mixed Parallel and Dataflow Architecture for Intra-prediction Hardware in HEVC Decoder
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    Chapter 71 A Formal Perspective on Effective Post-silicon Debug and Trace Signal Selection
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    Chapter 72 Translation Validation of Loop Invariant Code Optimizations Involving False Computations
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    Chapter 73 A Framework for Automated Feature Based Mixed-Signal Equivalence Checking
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    Chapter 74 xMAS Based Accurate Modeling and Progress Verification of NoCs
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    Chapter 75 Faulty TSVs Identification in 3D IC Using Pre-bond Testing