Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation

Table of Contents

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   Book Overview
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   Chapter 1 The First Quartz Electronic Watch
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   Chapter 2 An Improved Power Macro-Model for Arithmetic Datapath Components
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   Chapter 3 Performance Comparison of VLSI Adders Using Logical Effort
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   Chapter 4 MDSP: A High-Performance Low-Power DSP Architecture
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   Chapter 5 Impact of Technology in Power-Grid-Induced Noise
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   Chapter 6 Exploiting Metal Layer Characteristics for Low-Power Routing
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   Chapter 7 Crosstalk Measurement Technique for CMOS ICs
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   Chapter 8 Instrumentation Set-up for Instruction Level Power Modeling
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    Chapter 9 Low-Power Asynchronous A/D Conversion
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    Chapter 10 Optimal Two-Level Delay — Insensitive Implementation of Logic Functions
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    Chapter 11 Resonant Multistage Charging of Dominant Capacitances
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    Chapter 12 A New Methodology to Design Low-Power Asynchronous Circuits
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    Chapter 13 Designing Carry Look-Ahead Adders with an Adiabatic Logic Standard-Cell Library
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    Chapter 14 Clocking and Clocked Storage Elements in Multi-GHz Environment
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    Chapter 15 Dual Supply Voltage Scaling in a Conventional Power-Driven Logic Synthesis Environment
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    Chapter 16 Transistor Level Synthesis Dedicated to Fast I.P. Prototyping
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    Chapter 17 Robust SAT-Based Search Algorithm for Leakage Power Reduction
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    Chapter 18 PA-ZSA (Power-Aware Zero-Slack Algorithm): A Graph-Based Timing Analysis for Ultra-Low Power CMOS VLSI
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    Chapter 19 A New Methodology for Efficient Synchronization of RNS-Based VLSI Systems
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    Chapter 20 Clock Distribution Network Optimization under Self-Heating and Timing Constraints
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    Chapter 21 A Technique to Generate CMOS VLSI Flip-Flops Based on Differential Latches
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    Chapter 22 A Compact Charge-Based Propagation Delay Model for Submicronic CMOS Buffers
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    Chapter 23 Output Waveform Evaluation of Basic Pass Transistor Structure
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    Chapter 24 An Approach to Energy Consumption Modeling in RC Ladder Circuits
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    Chapter 25 Structure Independent Representation of Output Transition Time for CMOS Library
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    Chapter 26 A Low Energy Clustered Instruction Memory Hierarchy for Long Instruction Word Processors
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    Chapter 27 Design and Realization of a Low Power Register File Using Energy Model
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    Chapter 28 Register File Energy Reduction by Operand Data Reuse
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    Chapter 29 Energy-Efficient Design of the Reorder Buffer
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    Chapter 30 Trends in Ultralow-Voltage RAM Technology
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    Chapter 31 Offine Data Profiling Techniques to Enhance Memory Compression in Embedded Systems
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    Chapter 32 Performance and Power Comparative Study of Discrete Wavelet Transform on Programmable Processors
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    Chapter 33 Power Consumption Estimation of a C Program for Data-Intensive Applications
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    Chapter 34 A Low Overhead Auto-Optimizing Bus Encoding Scheme for Low Power Data Transmission
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    Chapter 35 Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level
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    Chapter 36 Low-Power FSMs in FPGA: Encoding Alternatives
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    Chapter 37 Synthetic Generation of Events for Address-Event-Representation Communications
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    Chapter 38 Reducing Energy Consumption via Low-Cost Value Prediction
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    Chapter 39 Dynamic Voltage Scheduling for Real Time Asynchronous Systems
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    Chapter 40 Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level
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    Chapter 41 Power Efficient Vector Quantization Design Using Pixel Truncation
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    Chapter 42 Minimizing Spurious Switching Activities in CMOS Circuits
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    Chapter 43 Modeling Propagation Delay of MUX, XOR, and D-Latch Source-Coupled Logic Gates
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    Chapter 44 Operating Region Modelling and Timing Analysis of CMOS Gates Driving Transmission Lines
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    Chapter 45 Selective Clock-Gating for Low Power/Low Noise Synchronous Counters
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    Chapter 46 Probabilistic Power Estimation for Digital Signal Processing Architectures
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    Chapter 47 Modeling of Propagation Delay of a First Order Circuit with a Ramp Input
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    Chapter 48 Characterization of Normal Propagation Delay for Delay Degradation Model (DDM)
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    Chapter 49 Automated Design Methodology for CMOS Analog Circuit Blocks in Complex Systems