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Applied Reconfigurable Computing. Architectures, Tools, and Applications

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Cover of 'Applied Reconfigurable Computing. Architectures, Tools, and Applications'

Table of Contents

  1. Altmetric Badge
    Book Overview
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    Chapter 1 Approximate FPGA-Based LSTMs Under Computation Time Constraints
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    Chapter 2 Redundancy-Reduced MobileNet Acceleration on Reconfigurable Logic for ImageNet Classification
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    Chapter 3 Accuracy to Throughput Trade-Offs for Reduced Precision Neural Networks on Reconfigurable Logic
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    Chapter 4 Deep Learning on High Performance FPGA Switching Boards: Flow-in-Cloud
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    Chapter 5 SqueezeJet: High-level Synthesis Accelerator Design for Deep Convolutional Neural Networks
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    Chapter 6 Efficient Hardware Acceleration of Recommendation Engines: A Use Case on Collaborative Filtering
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    Chapter 7 VerCoLib: Fast and Versatile Communication for FPGAs via PCI Express
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    Chapter 8 Lookahead Memory Prefetching for CGRAs Using Partial Loop Unrolling
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    Chapter 9 Performance Estimation of FPGA Modules for Modular Design Methodology Using Artificial Neural Network
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    Chapter 10 Achieving Efficient Realization of Kalman Filter on CGRA Through Algorithm-Architecture Co-design
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    Chapter 11 FPGA-Based Memory Efficient Shift-And Algorithm for Regular Expression Matching
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    Chapter 12 Towards an Optimized Multi FPGA Architecture with STDM Network: A Preliminary Study
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    Chapter 13 An FPGA/HMC-Based Accelerator for Resolution Proof Checking
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    Chapter 14 An Efficient FPGA Implementation of the Big Bang-Big Crunch Optimization Algorithm
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    Chapter 15 ReneGENE-GI: Empowering Precision Genomics with FPGAs on HPCs
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    Chapter 16 FPGA-Based Parallel Pattern Matching
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    Chapter 17 Embedded Vision Systems: A Review of the Literature
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    Chapter 18 A Survey of Low Power Design Techniques for Last Level Caches
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    Chapter 19 ISA-DTMR: Selective Protection in Configurable Heterogeneous Multicores
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    Chapter 20 Analyzing AXI Streaming Interface for Hardware Acceleration in AP-SoC Under Soft Errors
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    Chapter 21 High Performance UDP/IP 40Gb Ethernet Stack for FPGAs
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    Chapter 22 Tackling Wireless Sensor Network Heterogeneity Through Novel Reconfigurable Gateway Approach
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    Chapter 23 A Low-Power FPGA-Based Architecture for Microphone Arrays in Wireless Sensor Networks
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    Chapter 24 A Hybrid FPGA Trojan Detection Technique Based-on Combinatorial Testing and On-chip Sensing
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    Chapter 25 HoneyWiN: Novel Honeycomb-Based Wireless NoC Architecture in Many-Core Era
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    Chapter 26 Fast Partial Reconfiguration on SRAM-Based FPGAs: A Frame-Driven Routing Approach
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    Chapter 27 A Dynamic Partial Reconfigurable Overlay Framework for Python
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    Chapter 28 Runtime Adaptive Cache for the LEON3 Processor
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    Chapter 29 Exploiting Partial Reconfiguration on a Dynamic Coarse Grained Reconfigurable Architecture
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    Chapter 30 DIM-VEX: Exploiting Design Time Configurability and Runtime Reconfigurability
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    Chapter 31 The Use of HACP+SBT Lossless Compression in Optimizing Memory Bandwidth Requirement for Hardware Implementation of Background Modelling Algorithms
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    Chapter 32 A Reconfigurable PID Controller
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    Chapter 33 High-Level Synthesis of Software-Defined MPSoCs
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    Chapter 34 Improved High-Level Synthesis for Complex CellML Models
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    Chapter 35 An Intrusive Dynamic Reconfigurable Cycle-Accurate Debugging System for Embedded Processors
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    Chapter 36 Rapid Prototyping and Verification of Hardware Modules Generated Using HLS
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    Chapter 37 Comparing C and SystemC Based HLS Methods for Reconfigurable Systems Design
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    Chapter 38 Fast DSE for Automated Parallelization of Embedded Legacy Applications
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    Chapter 39 Control Flow Analysis for Embedded Multi-core Hybrid Systems
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    Chapter 40 A Low-Cost BRAM-Based Function Reuse for Configurable Soft-Core Processors in FPGAs
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    Chapter 41 A Parallel-Pipelined OFDM Baseband Modulator with Dynamic Frequency Scaling for 5G Systems
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    Chapter 42 Area-Energy Aware Dataflow Optimisation of Visual Tracking Systems
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    Chapter 43 Fast Carry Chain Based Architectures for Two’s Complement to CSD Recoding on FPGAs
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    Chapter 44 Exploring Functional Acceleration of OpenCL on FPGAs and GPUs Through Platform-Independent Optimizations
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    Chapter 45 ReneGENE-Novo: Co-designed Algorithm-Architecture for Accelerated Preprocessing and Assembly of Genomic Short Reads
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    Chapter 46 An OpenCL TM Implementation of WebP Accelerator on FPGAs
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    Chapter 47 Efficient Multitasking on FPGA Using HDL-Based Checkpointing
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    Chapter 48 High Level Synthesis Implementation of Object Tracking Algorithm on Reconfigurable Hardware
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    Chapter 49 Reconfigurable FPGA-Based Channelization Using Polyphase Filter Banks for Quantum Computing Systems
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    Chapter 50 Reconfigurable IP-Based Spectral Interference Canceller
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    Chapter 51 FPGA-Assisted Distribution Grid Simulator
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    Chapter 52 Analyzing the Use of Taylor Series Approximation in Hardware and Embedded Software for Good Cost-Accuracy Tradeoffs
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    Chapter 53 CGRA Tool Flow for Fast Run-Time Reconfiguration
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    Chapter 54 Seamless FPGA Deployment over Spark in Cloud Computing: A Use Case on Machine Learning Hardware Acceleration
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    Chapter 55 The ARAMiS Project Initiative
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    Chapter 56 Mapping and Scheduling Hard Real Time Applications on Multicore Systems - The ARGO Approach
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    Chapter 57 Robots in Assisted Living Environments as an Unobtrusive, Efficient, Reliable and Modular Solution for Independent Ageing: The RADIO Experience
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    Chapter 58 HLS Algorithmic Explorations for HPC Execution on Reconfigurable Hardware - ECOSCALE
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    Chapter 59 Supporting Utilities for Heterogeneous Embedded Image Processing Platforms (STHEM): An Overview
Overall attention for this book and its chapters
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Title
Applied Reconfigurable Computing. Architectures, Tools, and Applications
Published by
Springer International Publishing, June 2018
DOI 10.1007/978-3-319-78890-6
ISBNs
978-3-31-978889-0, 978-3-31-978890-6
Editors

Voros, Nikolaos, Huebner, Michael, Keramidas, Georgios, Goehringer, Diana, Antonopoulos, Christos, Diniz, Pedro C.

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The data shown below were collected from the profiles of 6 X users who shared this research output. Click here to find out more about how the information was compiled.
Mendeley readers

Mendeley readers

The data shown below were compiled from readership statistics for 22 Mendeley readers of this research output. Click here to see the associated Mendeley record.

Geographical breakdown

Country Count As %
Unknown 22 100%

Demographic breakdown

Readers by professional status Count As %
Student > Bachelor 2 9%
Student > Doctoral Student 1 5%
Student > Ph. D. Student 1 5%
Student > Master 1 5%
Researcher 1 5%
Other 1 5%
Unknown 15 68%
Readers by discipline Count As %
Computer Science 3 14%
Engineering 3 14%
Physics and Astronomy 1 5%
Unknown 15 68%