VLSI for Neural Networks and Artificial Intelligence

Table of Contents

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   Book Overview
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   Chapter 1 Analog VLSI Neural Learning Circuits — A Tutorial
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   Chapter 2 An Analog CMOS Implementation of a Kohonen Network with Learning Capability
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   Chapter 3 Back-Propagation Learning Algorithms for Analog VLSI Implementation
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   Chapter 4 An Analog Implementation of the Boltzmann Machine with Programmable Learning Algorithms
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   Chapter 5 A VLSI Design of the Minimum Entropy Neuron
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   Chapter 6 A Multi-Layer Analog VLSI Architecture for Texture Analysis Isomorphic to Cortical Cells in Mammalian Visual System
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   Chapter 7 A VLSI Pipelined Neuroemulator
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   Chapter 8 A Low Latency Digital Neural Network Architecture
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    Chapter 9 MANTRA: A Multi-Model Neural-Network Computer
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    Chapter 10 SPERT: A Neuro-Microprocessor
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    Chapter 11 Design of Neural Self-Organization Chips for Semantic Applications
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    Chapter 12 VLSI Implementation of a Digital Neural Network with Reward-Penalty Learning
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    Chapter 13 Asynchronous VLSI Design for Neural System Implementation
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    Chapter 14 VLSI-Implementation of Associative Memory Systems for Neural Information Processing
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    Chapter 15 A Dataflow Approach for Neural Networks
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    Chapter 16 A Custom Associative Chip Used as a Building Block for a Software Reconfigurable Multi-Network Simulator
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    Chapter 17 Parallel Implementation of Neural Associative Memories on RISC Processors
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    Chapter 18 Reconfigurable Logic Implementation of Memory-Based Neural Networks: A Case Study of the CMAC Network
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    Chapter 19 A Cascadable VLSI Design for GENET
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    Chapter 20 Parametrised Neural Network Design and Compilation into Hardware
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    Chapter 21 Knowledge Processing in Neural Architecture
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    Chapter 22 Two Methods for Solving Linear Equations Using Neural Networks
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    Chapter 23 Hardware Support for Data Parallelism in Production Systems
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    Chapter 24 SPACE: Symbolic Processing in Associative Computing Elements
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    Chapter 25 PALM: A Logic Programming System on a Highly Parallel Architecture
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    Chapter 26 A Distributed Parallel Associative Processor (DPAP) for the Execution of Logic Programs
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    Chapter 27 Performance Analysis of a Parallel VLSI Architecture for Prolog
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    Chapter 28 A Prolog VLSI System for Real Time Applications
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    Chapter 29 An Extended WAM Based Architecture for OR-Parallel Prolog Execution
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    Chapter 30 Architecture and VLSI Implementation of a Pegasus-II Prolog Processor