Applied Reconfigurable Computing

Table of Contents

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   Book Overview
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   Chapter 1 The VINEYARD Approach: Versatile, Integrated, Accelerator-Based, Heterogeneous Data Centres
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   Chapter 2 A Design Methodology for the Next Generation Real-Time Vision Processors
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   Chapter 3 EEG Feature Extraction Accelerator Enabling Long Term Epilepsy Monitoring Based on Ultra Low Power WSNs
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   Chapter 4 Computing to the Limit with Heterogeneous CPU-FPGA Devices in a Video Fusion Application
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   Chapter 5 An Efficient Hardware Architecture for Block Based Image Processing Algorithms
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   Chapter 6 An FPGA Stereo Matching Processor Based on the Sum of Hamming Distances
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   Chapter 7 FPGA Soft-Core Processors, Compiler and Hardware Optimizations Validated Using HOG
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   Chapter 8 A Comparison of Machine Learning Classifiers for FPGA Implementation of HOG-Based Human Detection
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    Chapter 9 A Scalable Dataflow Accelerator for Real Time Onboard Hyperspectral Image Classification
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    Chapter 10 A Redundant Design Approach with Diversity of FPGA Resource Mapping
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    Chapter 11 Method to Analyze the Susceptibility of HLS Designs in SRAM-Based FPGAs Under Soft Errors
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    Chapter 12 Low Cost Dynamic Scrubbing for Real-Time Systems
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    Chapter 13 Analytical Delay Model for CPU-FPGA Data Paths in Programmable System-on-Chip FPGA
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    Chapter 14 New Partitioning Approach for Hardware Trojan Detection Using Side-Channel Measurements
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    Chapter 15 A Comprehensive Set of Schemes for PUF Response Generation
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    Chapter 16 Design and Optimization of Digital Circuits by Artificial Evolution Using Hybrid Multi Chromosome Cartesian Genetic Programming
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    Chapter 17 A Multi-codec Framework to Enhance Data Channels in FPGA Streaming Systems
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    Chapter 18 Reconfigurable FPGA-Based FFT Processor for Cognitive Radio Applications
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    Chapter 19 Real-Time Audio Group Delay Correction with FFT Convolution on FPGA
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    Chapter 20 Comparing Register-Transfer-, C-, and System-Level Implementations of an Image Enhancement Algorithm
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    Chapter 21 Evaluating Schedulers in a Reconfigurable Multicore Heterogeneous System
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    Chapter 22 Programmable Logic as Device Virtualization Layer in Heterogeneous Multicore Architectures
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    Chapter 23 Zynq Cluster for CFD Parametric Survey
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    Chapter 24 Fast and Resource Aware Image Processing Operators Utilizing Highly Configurable IP Blocks
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    Chapter 25 Performance Evaluation of Feed-Forward Backpropagation Neural Network for Classification on a Reconfigurable Hardware Architecture
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    Chapter 26 FPGA-Based Acceleration of Pattern Matching in YARA
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    Chapter 27 Efficient Camera Input System and Memory Partition for a Vision Soft-Processor
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    Chapter 28 A Lost Cycles Analysis for Performance Prediction using High-Level Synthesis
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    Chapter 29 A Dynamic Cache Architecture for Efficient Memory Resource Allocation in Many-Core Systems
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    Chapter 30 Adaptive Bandwidth Router for 3D Network-on-Chips
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    Chapter 31 Reduced-precision Algorithm-based Fault Tolerance for FPGA-implemented Accelerators