Applied Reconfigurable Computing. Architectures, Tools, and Applications

Chapter 1 Improving Performance Estimation for FPGA-Based Accelerators for Convolutional Neural Networks

Chapter 2 Judiciously Spreading Approximation Among Arithmetic Components with Top-Down Inexact Hardware Design

Chapter 3 Optimising Operator Sets for Analytical Database Processing on FPGAs

Chapter 4 Automated Toolchain for Enhanced Productivity in Reconfigurable Multi-accelerator Systems

Chapter 5 Chisel Usecase: Designing General Matrix Multiply for FPGA

Chapter 6 Cycle-Accurate Debugging of Embedded Designs Using Recurrent Neural Networks

Chapter 7 Soft-Error Analysis of Self-reconfiguration Controllers for Safety Critical Dynamically Reconfigurable FPGAs

Chapter 8 SysIDLib: A High-Level Synthesis FPGA Library for Online System Identification

Chapter 9 Optimal and Greedy Heuristic Approaches for Scheduling and Mapping of Hardware Tasks to Reconfigurable Computing Devices

Chapter 10 Accuracy, Training Time and Hardware Efficiency Trade-Offs for Quantized Neural Networks on FPGAs

Chapter 11 Accelerating a Classic 3D Video Game on Heterogeneous Reconfigurable MPSoCs

Chapter 12 Cross-layer CNN Approximations for Hardware Implementation

Chapter 13 Technique for Vendor and Device Agnostic Hardware Area-Time Estimation

Chapter 14 Resource Efficient Dynamic Voltage and Frequency Scaling on Xilinx FPGAs

Chapter 15 RISC-V Based MPSoC Design Exploration for FPGAs: Area, Power and Performance

Chapter 16 A Modular Software Library for Effective High Level Synthesis of Convolutional Neural Networks

Chapter 17 HLS-Based Acceleration Framework for Deep Convolutional Neural Networks

Chapter 18 FPGA-Based Computational Fluid Dynamics Simulation Architecture via High-Level Synthesis Design Method

Chapter 19 High-Level Synthesis in Implementing and Benchmarking Number Theoretic Transform in Lattice-Based Post-Quantum Cryptography Using Software/Hardware Codesign

Chapter 20 Exploring fpga Optimizations to Compute Sparse Numerical Linear Algebra Kernels

Chapter 21 A CGRA Definition Framework for Dataflow Applications

Chapter 22 Implementing CNNs Using a Linear Array of Full Mesh CGRAs

Chapter 23 A Block-Based Systolic Array on an HBM2 FPGA for DNA Sequence Alignment

Chapter 24 Comparison of Direct and Indirect Networks for High-Performance FPGA Clusters

Chapter 26 Hardware/Algorithm Co-optimization for Fully-Parallelized Compact Decision Tree Ensembles on FPGAs

Chapter 27 StocNoC: Accelerating Stochastic Models Through Reconfigurable Network on Chip Architectures

Chapter 28 Implementation of FM-Index Based Pattern Search on a Multi-FPGA System

Chapter 29 Reconfigurable Accelerator for On-Board SAR Imaging Using the Backprojection Algorithm