An Analytical Programming Model for the Drain-Coupling Source-Side Injection Split Gate Flash Eeprom

Overview of attention for article published in IEEE Transactions on Electron Devices, March 2005

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ARTIFICIAL NEURAL NETWORK COMPRISING REFERENCE ARRAY FOR I-V SLOPE CONFIGURATION

Application US-20230325646-A1

United States of America

The program timing sequence circuit and method of separate gate flash memory

Application CN-108597554-A

China

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