Logic transformation for low power synthesis

Overview of attention for article published in this source, January 1999

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Power gating logic cones

Grant US-7873923-B2

United States of America

Method and apparatus for physical implementation of a power optimized circuit design

Grant US-7840918-B1

United States of America

Method of modeling and employing the CMOS gate slew and output load dependent pin…

Grant US-7788617-B2

United States of America

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