A Hierarchical Test Scheme for System-on-Chip Designs

Overview of attention for article published in this source, January 2002

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Device testing architecture, method, and system

Grant US-10281526-B2

United States of America

Test device and method for the SoC test architecture

Grant US-8555123-B2

United States of America

Test device and method for hierarchical test architecture

Grant US-8185782-B2

United States of America

Integrated circuit and method for testing memory on the integrated circuit

Grant US-8145958-B2

United States of America

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