A customized design of DRAM controller for on-chip 3D DRAM stacking

Overview of attention for article published in this source, September 2010

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Memory package having stacked array dies and reduced driver load

Grant US-12646537-B1

United States of America

Memory package having stacked array dies and reduced driver load

Grant US-12308087-B2

United States of America

Memory module with buffered memory packages

Grant US-10902886-B2

United States of America

Memory module with packages of stacked memory chips

Grant US-10290328-B2

United States of America

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