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High Performance Dual-Gate ISFET with Non-Ideal Effect Reduction Schemes in a SOI-CMOS Bioelectrical SoC

Overview of attention for article published in this source, December 2015
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9 patents

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67 Mendeley
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Article details
Title
High Performance Dual-Gate ISFET with Non-Ideal Effect Reduction Schemes in a SOI-CMOS Bioelectrical SoC
Published by
Institute of Electrical and Electronics Engineers (IEEE), December 2015
DOI 10.1109/iedm.2015.7409792
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Mendeley demographics

Mendeley demographics

The data shown below were compiled from readership statistics for 67 Mendeley readers of this research output. Click here to see the associated Mendeley record.
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Geographical breakdown

Geographical breakdown
Country Count As %
Unknown 67 100%

Demographic breakdown

Readers by professional status
Readers by professional status Count As %
Student > Ph. D. Student 22 33%
Researcher 15 22%
Student > Master 8 12%
Student > Doctoral Student 4 6%
Professor 4 6%
Other 4 6%
Unknown 10 15%
Readers by discipline
Readers by discipline Count As %
Engineering 37 55%
Materials Science 10 15%
Physics and Astronomy 4 6%
Agricultural and Biological Sciences 2 3%
Computer Science 1 1%
Other 0 0%
Unknown 13 19%