Three-dimensional 4F2 ReRAM cell with CMOS logic compatible process

Overview of attention for article published in International Electron Devices Meeting 1998 Technical Digest (Cat No98CH36217), December 2010

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Underlying transistor circuit of semiconductor memory and preparation method for the same

Grant US-12505866-B2

United States of America

Three-dimensional stackable multi-layer cross-point memory with bipolar junction…

Grant US-11018188-B2

United States of America

Three-dimensional stackable multi-layer cross-point memory with single-crystalline…

Grant US-10903275-B2

United States of America

Resistive memory with amorphous silicon filaments

Grant US-10741754-B2

United States of America

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