Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation

Table of Contents

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   Book Overview
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   Chapter 1 Subthreshold FIR Filter Architecture for Ultra Low Power Applications
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   Chapter 2 Reverse Vgs Static CMOS (RVGS-SCMOS); A New Technique for Dynamically Compensating the Process Variations in Sub-threshold Designs
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   Chapter 3 Improving the Power-Delay Performance in Subthreshold Source-Coupled Logic Circuits
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   Chapter 4 Design and Evaluation of Mixed 3T-4T FinFET Stacks for Leakage Reduction
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   Chapter 5 Temporal Discharge Current Driven Clustering for Improved Leakage Power Reduction in Row-Based Power-Gating
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   Chapter 6 Intelligate: Scalable Dynamic Invariant Learning for Power Reduction
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   Chapter 7 Analysis of Effects of Input Arrival Time Variations on On-Chip Bus Power Consumption
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   Chapter 8 Power-Aware Design via Micro-architectural Link to Implementation
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    Chapter 9 Untraditional Approach to Computer Energy Reduction
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    Chapter 10 Mixed Radix-2 and High-Radix RNS Bases for Low-Power Multiplication
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    Chapter 11 Power Optimization of Parallel Multipliers in Systems with Variable Word-Length
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    Chapter 12 A Design Space Comparison of 6T and 8T SRAM Core-Cells
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    Chapter 13 Latched CMOS DRAM Sense Amplifier Yield Analysis and Optimization
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    Chapter 14 Understanding the Effect of Intradie Random Process Variations in Nanometer Domino Logic
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    Chapter 15 A Study on CMOS Time Uncertainty with Technology Scaling
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    Chapter 16 Static Timing Model Extraction for Combinational Circuits
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    Chapter 17 A New Bounding Technique for Handling Arbitrary Correlations in Path-Based SSTA
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    Chapter 18 Statistical Modeling and Analysis of Static Leakage and Dynamic Switching Power
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    Chapter 19 Logic Synthesis of Handshake Components Using Structural Clustering Techniques
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    Chapter 20 Fast Universal Synchronizers
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    Chapter 21 A Performance-Driven Multilevel Framework for the X-Based Full-Chip Router
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    Chapter 22 PMD: A Low-Power Code for Networks-on-Chip Based on Virtual Channels
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    Chapter 23 Near-Field Mapping System to Scan in Time Domain the Magnetic Emissions of Integrated Circuits
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    Chapter 24 A Comparison between Two Logic Synthesis Forms from Digital Switching Noise Viewpoint
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    Chapter 25 Generating Worst-Case Stimuli for Accurate Power Grid Analysis
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    Chapter 26 Monolithic Multi-mode DC-DC Converter with Gate Voltage Optimization
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    Chapter 27 Energy Efficiency of Power-Gating in Low-Power Clocked Storage Elements
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    Chapter 28 A New Dynamic Logic Circuit Design for an Effective Trade-Off between Noise-Immunity, Performance and Energy Dissipation
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    Chapter 29 Energy Efficient Elliptic Curve Processor
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    Chapter 30 Energy Efficient Coarse-Grain Reconfigurable Array for Accelerating Digital Signal Processing
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    Chapter 31 Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures
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    Chapter 32 Settling-Optimization-Based Design Approach for Three-Stage Nested-Miller Amplifiers
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    Chapter 33 Ultra Low Voltage High Speed Differential CMOS Inverter
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    Chapter 34 Differential Capacitance Analysis
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    Chapter 35 Automated Synchronous-to-Asynchronous Circuits Conversion: A Survey
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    Chapter 36 Novel Cross-Transition Elimination Technique Improving Delay and Power Consumption for On-Chip Buses
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    Chapter 37 Analytical High-Level Power Model for LUT-Based Components
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    Chapter 38 A Formal Approach for Estimating Embedded System Execution Time and Energy Consumption
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    Chapter 39 Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates
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    Chapter 40 Disjoint Region Partitioning for Probabilistic Switching Activity Estimation at Register Transfer Level
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    Chapter 41 Data Dependence of Delay Distribution for a Planar Bus
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    Chapter 42 Towards Novel Approaches in Design Automation for FPGA Power Optimization
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    Chapter 43 Smart Enumeration: A Systematic Approach to Exhaustive Search
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    Chapter 44 An Efficient Approach for Managing Power Consumption Hotspots Distribution on 3D FPGAs
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    Chapter 45 Interconnect Power Analysis for a Coarse-Grained Reconfigurable Array Processor
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    Chapter 46 Integration of Power Management Units onto the SoC
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    Chapter 47 Model to Hardware Matching for nm Scale Technologies
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    Chapter 48 Power and Profit: Engineering in the Envelope