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Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation

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Cover of 'Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation'

Table of Contents

  1. Altmetric Badge
    Book Overview
  2. Altmetric Badge
    Chapter 1 Robust Low Power Embedded SRAM Design: From System to Memory Cell
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    Chapter 2 Variability in Advanced Nanometer Technologies: Challenges and Solutions
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    Chapter 3 Subthreshold Circuit Design for Ultra-Low-Power Applications
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    Chapter 4 SystemC AMS Extensions: New Language – New Methods – New Applications
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    Chapter 5 Process Variation Aware Performance Analysis of Asynchronous Circuits Considering Spatial Correlation
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    Chapter 6 Interpreting SSTA Results with Correlation
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    Chapter 7 Residue Arithmetic for Variation-Tolerant Design of Multiply-Add Units
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    Chapter 8 Exponent Monte Carlo for Quick Statistical Circuit Simulation
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    Chapter 9 Clock Repeater Characterization for Jitter-Aware Clock Tree Synthesis
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    Chapter 10 A Hardware Implementation of the User-Centric Display Energy Management
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    Chapter 11 On-chip Thermal Modeling Based on SPICE Simulation
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    Chapter 12 Switching Noise Optimization in the Wake-Up Phase of Leakage-Aware Power Gating Structures
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    Chapter 13 Application-Specific Temperature Reduction Systematic Methodology for 2D and 3D Networks-on-Chip
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    Chapter 14 Data-Driven Clock Gating for Digital Filters
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    Chapter 15 Power Management and Its Impact on Power Supply Noise
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    Chapter 16 Assertive Dynamic Power Management (AsDPM) Strategy for Globally Scheduled RT Multiprocessor Systems
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    Chapter 17 Design Optimization of Low-Power 90nm CMOS SOC Application Using 0.5V Bulk PMOS Dynamic-Threshold with Dual Threshold (MTCMOS): BP-DTMOS-DT Technique
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    Chapter 18 Crosstalk in High-Performance Asynchronous Designs
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    Chapter 19 Modeling and Reducing EMI in GALS and Synchronous Systems
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    Chapter 20 Low-Power Dual-Edge Triggered State Retention Scan Flip-Flop
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    Chapter 21 Multi-granularity NoC Simulation Framework for Early Phase Exploration of SDR Hardware Platforms
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    Chapter 22 Dynamic Data Type Optimization and Memory Assignment Methodologies
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    Chapter 23 Accelerating Embedded Software Power Profiling Using Run-Time Power Emulation
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    Chapter 24 Write Invalidation Analysis in Chip Multiprocessors
  26. Altmetric Badge
    Chapter 25 Practical Design Space Exploration of an H264 Decoder for Handheld Devices Using a Virtual Platform
  27. Altmetric Badge
    Chapter 26 BSAA: A Switching Activity Analysis and Visualisation Tool for SoC Power Optimisation
  28. Altmetric Badge
    Chapter 27 Reducing Timing Overhead in Simultaneously Clock-Gated and Power-Gated Designs by Placement-Aware Clustering
  29. Altmetric Badge
    Chapter 28 Low Energy Voltage Dithering in Dual V DD Circuits
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    Chapter 29 Product On-Chip Process Compensation for Low Power and Yield Enhancement
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    Chapter 30 Low-Power Soft Error Hardened Latch
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    Chapter 31 Digital Timing Slack Monitors and Their Specific Insertion Flow for Adaptive Compensation of Variabilities
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    Chapter 32 Quasi-Delay-Insensitive Computing Device: Methodological Aspects and Practical Implementation
  34. Altmetric Badge
    Chapter 33 The Magic Rule of Tiles: Virtual Delay Insensitivity
  35. Altmetric Badge
    Chapter 34 Analysis of Power Consumption Using a New Methodology for the Capacitance Modeling of Complex Logic Gates
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    Chapter 35 A New Methodology for Power-Aware Transistor Sizing: Free Power Recovery (FPR)
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    Chapter 36 Routing Resistance Influence in Loading Effect on Leakage Analysis
  38. Altmetric Badge
    Chapter 37 Processor Customization for Software Implementation of the AES Algorithm for Wireless Sensor Networks
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    Chapter 38 An On-Chip Multi-mode Buck DC-DC Converter for Fine-Grain DVS on a Multi-power Domain SoC Using a 65-nm Standard CMOS Logic Process
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    Chapter 39 Energy Dissipation Reduction of a Cardiac Event Detector in the Sub-V t Domain By Architectural Folding
  41. Altmetric Badge
    Chapter 40 A New Optimized High-Speed Low-Power Data-Driven Dynamic (D3L) 32-Bit Kogge-Stone Adder
Attention for Chapter 29: Product On-Chip Process Compensation for Low Power and Yield Enhancement
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Chapter title
Product On-Chip Process Compensation for Low Power and Yield Enhancement
Chapter number 29
Book title
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Published by
Springer, Berlin, Heidelberg, September 2009
DOI 10.1007/978-3-642-11802-9_29
Book ISBNs
978-3-64-211801-2, 978-3-64-211802-9
Authors

Nabila Moubdi, Philippe Maurine, Robin Wilson, Nadine Azemard, Vincent Dumettier, Abhishek Bansal, Sebastien Barasinski, Alain Tournier, Guy Durieu, David Meyer, Pierre Busson, Sarah Verhaeren, Sylvain Engels, Moubdi, Nabila, Maurine, Philippe, Wilson, Robin, Azemard, Nadine, Dumettier, Vincent, Bansal, Abhishek, Barasinski, Sebastien, Tournier, Alain, Durieu, Guy, Meyer, David, Busson, Pierre, Verhaeren, Sarah, Engels, Sylvain

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Unknown 1 100%

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Readers by professional status Count As %
Student > Master 1 100%
Readers by discipline Count As %
Engineering 1 100%