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Formal Equivalence Checking and Design Debugging

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Cover of 'Formal Equivalence Checking and Design Debugging'

Table of Contents

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    Book Overview
  2. Altmetric Badge
    Chapter 1 Introduction
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    Chapter 2 Symbolic Verification
  4. Altmetric Badge
    Chapter 3 Incremental Verification for Combinational Circuits
  5. Altmetric Badge
    Chapter 4 Incremental Verification for Sequential Circuits
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    Chapter 5 AQUILA: A Local BDD-based Equivalence Verifier
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    Chapter 6 Algorithm for Verifying Retimed Circuits
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    Chapter 7 RTL-to-Gate Verification
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    Chapter 8 Introduction to Logic Debugging
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    Chapter 9 ErrorTracer: Error Diagnosis by Fault Simulation
  11. Altmetric Badge
    Chapter 10 Extension to Sequential Error Diagnosis
  12. Altmetric Badge
    Chapter 11 Incremental Logic Rectification
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Title
Formal Equivalence Checking and Design Debugging
Published by
Springer US, December 2012
DOI 10.1007/978-1-4615-5693-0
ISBNs
978-1-4613-7606-4, 978-1-4615-5693-0
Authors

Huang, Shi-Yu, Cheng, Kwang-Ting (Tim)

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