Cell height driven transistor sizing in a cell based static CMOS module design

Overview of attention for article published in IEEE Journal of Solid-State Circuits, May 1996

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Timing closure methodology including placement with initial delay values

Grant US-9811624-B2

United States of America

Timing closure methodology including placement with initial delay values

Grant US-8621403-B2

United States of America

Timing closure methodology

Application US-20050120319-A1

United States of America

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