On Delay Fault Testing in Logic Circuits

Overview of attention for article published in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, September 1987

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Electronic design automation tool and method for employing unsensitized critical path…

Grant US-8464198-B1

United States of America

Delay fault testing with IEEE 1149.1

Grant US-6286119-B1

United States of America

Method and system for identifying tested path delay faults

Grant US-6131181-A

United States of America

Robust delay fault built-in self-testing method and apparatus

Grant US-5422891-A

United States of America

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