A row-based cell placement method that utilizes circuit structural properties

Overview of attention for article published in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, March 1995

Altmetric Badge

Mentioned by

patent: 7 patents

Readers on

mendeley: 2 Mendeley

So far, Altmetric has seen 7 patents that reference this research output.

Detailed placer for optimizing high density cell placement in a linear runtime

Grant US-8069429-B2

United States of America

Detailed placer for optimizing high density cell placement in a linear runtime

Grant US-7404168-B2

United States of America

Detailed placer for optimizing high density cell placement in a linear runtime

Grant US-7036103-B2

United States of America

Updating placement during technology mapping

Grant US-6405345-B1

United States of America

This page shows the most recent patents that mention this research output. Click here to find out how to access more activity, including 3 additional patents.