A fast transistor-chaining algorithm for CMOS cell layout

Overview of attention for article published in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, July 1990

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patent: 5 patents

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So far, Altmetric has seen 5 patents that reference this research output.

System and method to generate re-useable layout components from schematic components in…

Grant US-8719754-B1

United States of America

06 May 2014

System and method for abutment in the presence of dummy shapes

Grant US-8694941-B1

United States of America

08 Apr 2014

Device level layout optimization in electronic design automation

Grant US-6671866-B2

United States of America

30 Dec 2003

DEVICE LEVEL LAYOUT OPTIMIZATION IN ELECTRONIC DESIGN AUTOMATION

Application WO-2001065424-A3

World Intellectual Property Organisation (WIPO)

23 Jan 2003

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