Method and apparatus for nested instruction looping using implicit predicates Grant US-7945768-B2 United States of America 17 May 2011
Method and apparatus for elimination of prolog and epilog instructions in a vector… Grant US-7415601-B2 United States of America 19 Aug 2008
Dataflow graph compression for power reduction in a vector processor Grant US-7290122-B2 United States of America 30 Oct 2007
Streaming vector processor with reconfigurable interconnection switch Grant US-7159099-B2 United States of America 02 Jan 2007