An efficient layout style for two-metal CMOS leaf cells and its automatic synthesis

Overview of attention for article published in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, March 1993

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Method and apparatus to optimize an integrated circuit design using transistor folding

Grant US-6968524-B2

United States of America

2-dimensional placement with reliability constraints for VLSI design

Grant US-6823500-B1

United States of America

Polygon representation in an integrated circuit layout

Grant US-6128767-A

United States of America

Method for generating transistor placement in an automatic cell layout design

Grant US-5995734-A

United States of America

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