Fast and Optimal Redundant Via Insertion

Overview of attention for article published in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, December 2008

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Method and apparatus of an integrated circuit

Grant US-8689160-B2

United States of America

Method and apparatus of an integrated circuit

Grant US-8522186-B2

United States of America

Redundant micro-loop structure for use in an integrated circuit physical design process…

Grant US-8234594-B2

United States of America

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