Delay bound based CMOS gate sizing technique

Alexandre Verle, Xavier Michel, Philippe Maurine, Nadine Azemard, Daniel Auvergne. Delay Bound Based CMOS Gate Sizing Technique. ISCAS: International Symposium on Circuits and Systems, May 2004, Vancouver, BC, Canada. pp.189-192, ⟨10.1109/ISCAS.2004.13294

HAL Archives-Ouvertes, 11 Sep 2019

Alexandre Verle, Xavier Michel, Philippe Maurine, Nadine Azemard, Daniel Auvergne.