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Memory-Logic Hybrid Gate with 3D-Stackable Complementary Latches for FinFET-based Neural Networks

Overview of attention for article published in this source, December 2019
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Article details
Title
Memory-Logic Hybrid Gate with 3D-Stackable Complementary Latches for FinFET-based Neural Networks
Published by
Institute of Electrical and Electronics Engineers (IEEE), December 2019
DOI 10.1109/iedm19573.2019.8993511
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Timeline Attention over time Attention Score history
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Mendeley demographics

Mendeley demographics

The data shown below were compiled from readership statistics for 34 Mendeley readers of this research output. Click here to see the associated Mendeley record.
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Geographical breakdown

Geographical breakdown
Country Count As %
Unknown 34 100%

Demographic breakdown

Readers by professional status
Readers by professional status Count As %
Researcher 10 29%
Student > Master 5 15%
Student > Doctoral Student 4 12%
Student > Ph. D. Student 4 12%
Professor 2 6%
Other 1 3%
Unknown 8 24%
Readers by discipline
Readers by discipline Count As %
Engineering 18 53%
Physics and Astronomy 4 12%
Biochemistry, Genetics and Molecular Biology 1 3%
Computer Science 1 3%
Earth and Planetary Sciences 1 3%
Other 1 3%
Unknown 8 24%