Method and apparatus to optimize an integrated circuit design using transistor folding Grant US-6968524-B2 United States of America 22 Nov 2005
2-dimensional placement with reliability constraints for VLSI design Grant US-6823500-B1 United States of America 23 Nov 2004
Method and apparatus for transistor optimization, method and apparatus for layout design… Grant US-6415417-B1 United States of America 02 Jul 2002