A Study of Self-Aligned Nitride Erasable OTP Cell by 45-nm CMOS Fully Compatible Process

Overview of attention for article published in IEEE Transactions on Electron Devices, April 2009

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Memory device and operating method thereof

Grant US-12387792-B2

United States of America

Dielectric fuse memory circuit and operation method thereof

Grant US-10127993-B2

United States of America

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