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Hardware co-simulation for a low complexity PAPR reduction scheme on an FPGA

Overview of attention for article published in International Journal of Wireless and Mobile Computing, January 2017
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Title
Hardware co-simulation for a low complexity PAPR reduction scheme on an FPGA
Published in
International Journal of Wireless and Mobile Computing, January 2017
DOI 10.1504/ijwmc.2017.083053
Authors

Khalid Al Hussaini, Borhanuddin M. Ali, Pooria Varahram, Shaiful J. Hashim, Ronan Farrell

Mendeley readers

The data shown below were compiled from readership statistics for 2 Mendeley readers of this research output. Click here to see the associated Mendeley record.

Geographical breakdown

Country Count As %
Unknown 2 100%

Demographic breakdown

Readers by professional status Count As %
Professor > Associate Professor 1 50%
Unknown 1 50%
Readers by discipline Count As %
Engineering 1 50%
Unknown 1 50%