↓ Skip to main content

Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream : 12th International Conference, FPL 2002 Montpellier, France, September 2–4, 2002 Proceedings

Overview of attention for book
Cover of 'Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream : 12th International Conference, FPL 2002 Montpellier, France, September 2–4, 2002 Proceedings'

Table of Contents

  1. Altmetric Badge
    Book Overview
  2. Altmetric Badge
    Chapter 1 The Age of Adaptive Computing Is Here
  3. Altmetric Badge
    Chapter 2 Disruptive Trends by Data-Stream-Based Computing
  4. Altmetric Badge
    Chapter 3 Multithreading for Logic-Centric Systems
  5. Altmetric Badge
    Chapter 4 Fast Prototyping with Co-operation of Simulation and Emulation
  6. Altmetric Badge
    Chapter 5 How Fast Is Rapid FPGA-based Prototyping: Lessons and Challenges from the Digital TV Design Prototyping Project
  7. Altmetric Badge
    Chapter 6 Implementing Asynchronous Circuits on LUT Based FPGAs
  8. Altmetric Badge
    Chapter 7 A Technique for FPGA Synthesis Driven by Automatic Source Code Analysis and Transformations
  9. Altmetric Badge
    Chapter 8 Flexible Routing Architecture Generation for Domain-Specific Reconfigurable Subsystems
  10. Altmetric Badge
    Chapter 9 iPACE-V1: A Portable Adaptive Computing Engine for Real Time Applications
  11. Altmetric Badge
    Chapter 10 Field-Programmable Custom Computing Machines - A Taxonomy -
  12. Altmetric Badge
    Chapter 11 Embedded Reconfigurable Logic Core for DSP Applications
  13. Altmetric Badge
    Chapter 12 Efficient FPGA-based QPSK Demodulation Loops: Application to the DVB Standard
  14. Altmetric Badge
    Chapter 13 FPGA QAM Demodulator Design
  15. Altmetric Badge
    Chapter 14 Analytical Framework for Switch Block Design
  16. Altmetric Badge
    Chapter 15 Modular, Fabric-Specific Synthesis for Programmable Architectures
  17. Altmetric Badge
    Chapter 16 On Optimum Designs of Universal Switch Blocks
  18. Altmetric Badge
    Chapter 17 Improved Functional Simulation of Dynamically Reconfigurable Logic
  19. Altmetric Badge
    Chapter 18 Run-Time Reconfiguration to Check Temperature in Custom Computers: An Application of JBits Technology
  20. Altmetric Badge
    Chapter 19 Dynamic Reconfiguration in Mobile Systems
  21. Altmetric Badge
    Chapter 20 Using PARBIT to Implement Partial Run-Time Reconfigurable Systems
  22. Altmetric Badge
    Chapter 21 Multiplier-less Realization of a Poly-phase Filter Using LUT-based FPGAs
  23. Altmetric Badge
    Chapter 22 Speech Recognition on an FPGA Using Discrete and Continuous Hidden Markov Models
  24. Altmetric Badge
    Chapter 23 FPGA Implementation of the Wavelet Packet Transform for High Speed Communications
  25. Altmetric Badge
    Chapter 24 A Method for Implementing Bit-Serial Finite Impulse Response Digital Filters in FPGAs Using JBits™
  26. Altmetric Badge
    Chapter 25 Automatic Partitioning for Improved Placement and Routing in Complex Programmable Logic Devices
  27. Altmetric Badge
    Chapter 26 Rapid and Reliable Routability Estimation for FPGAs
  28. Altmetric Badge
    Chapter 27 Integrated Iterative Approach to FPGA Placement
  29. Altmetric Badge
    Chapter 28 TDR: A Distributed-Memory Parallel Routing Algorithm for FPGAs
  30. Altmetric Badge
    Chapter 29 High-Level Partitioning of Digital Systems Based on Dynamically Reconfigurable Devices
  31. Altmetric Badge
    Chapter 30 High Speed Homology Search Using Run-Time Reconfiguration
  32. Altmetric Badge
    Chapter 31 Partially Reconfigurable Cores for Xilinx Virtex
  33. Altmetric Badge
    Chapter 32 On-line Defragmentation for Run-Time Partially Reconfigurable FPGAs
  34. Altmetric Badge
    Chapter 33 A Flexible Power Model for FPGAs
  35. Altmetric Badge
    Chapter 34 Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream
  36. Altmetric Badge
    Chapter 35 Energy Evaluation on a Reconfigurable, Multimedia-Oriented Wireless Sensor
  37. Altmetric Badge
    Chapter 36 A Tool for Activity Estimation in FPGAs
  38. Altmetric Badge
    Chapter 37 FSM Decomposition for Low Power in FPGA
  39. Altmetric Badge
    Chapter 38 Hybrid Routing for FPGAs by Integrating Boolean Satisfiability with Geometric Search
  40. Altmetric Badge
    Chapter 39 A Prolog-Based Hardware Development Environment
  41. Altmetric Badge
    Chapter 40 Fly — A Modifiable Hardware Compiler
  42. Altmetric Badge
    Chapter 41 Challenges and Opportunities for FPGA Platforms
  43. Altmetric Badge
    Chapter 42 Design and Implementation of FPGA Circuits for High Speed Network Monitors
  44. Altmetric Badge
    Chapter 43 Granidt: Towards Gigabit Rate Network Intrusion Detection Technology
  45. Altmetric Badge
    Chapter 44 Fast SiGe HBT BiCMOS FPGAs with New Architecture and Power Saving Techniques
  46. Altmetric Badge
    Chapter 45 Field-Programmable Analog Arrays: A Floating—Gate Approach
  47. Altmetric Badge
    Chapter 46 A Generalized Execution Model for Programming on Reconfigurable Architectures and an Architecture Supporting the Model
  48. Altmetric Badge
    Chapter 47 A Framework for Teaching (Re)Configurable Architectures in Student Projects
  49. Altmetric Badge
    Chapter 48 Specialized Hardware for Deep Network Packet Filtering
  50. Altmetric Badge
    Chapter 49 Implementation of a Successive Erasure BCH (16,7,6) Decoder and Performance Simulation by Rapid Prototyping
  51. Altmetric Badge
    Chapter 50 Fast RNS FPL-based Communications Receiver Design and Implementation
  52. Altmetric Badge
    Chapter 51 UltraSONIC: A Reconfigurable Architecture for Video Image Processing
  53. Altmetric Badge
    Chapter 52 Implementing the Discrete Cosine Transform Using the Xilinx Virtex FPGA
  54. Altmetric Badge
    Chapter 53 Implementation of the JPEG 2000 Standard on a Virtex 1000 FPGA
  55. Altmetric Badge
    Chapter 54 Small Multiplier-Based Multiplication and Division Operators for Virtex-II Devices
  56. Altmetric Badge
    Chapter 55 Automating Customisation of Floating-Point Designs
  57. Altmetric Badge
    Chapter 56 Energy-Efficient Matrix Multiplication on FPGAs
  58. Altmetric Badge
    Chapter 57 Run-Time Adaptive Flexible Instruction Processors
  59. Altmetric Badge
    Chapter 58 DARP — A Digital Audio Reconfigurable Processor
  60. Altmetric Badge
    Chapter 59 System-Level Modelling for Performance Estimation of Reconfigurable Coprocessors
  61. Altmetric Badge
    Chapter 60 An FPGA Based SHA-256 Processor
  62. Altmetric Badge
    Chapter 61 Handling FPGA Faults and Configuration Sequencing Using a Hardware Extension
  63. Altmetric Badge
    Chapter 62 On the Set of Target Path Delay Faults in Sequential Subcircuits of LUT-based FPGAs
  64. Altmetric Badge
    Chapter 63 Simulation-Based Analysis of SEU Effects on SRAM-based FPGAs
  65. Altmetric Badge
    Chapter 64 Exploiting Reconfigurability for Effective Testing of Delay Faults in Sequential Subcircuits of LUT-based FPGAs
  66. Altmetric Badge
    Chapter 65 Logarithmic Number System and Floating-Point Arithmetics on FPGA
  67. Altmetric Badge
    Chapter 66 Novel Optimizations for Hardware Floating-Point Units in a Modern FPGA Architecture
  68. Altmetric Badge
    Chapter 67 Morphable Multipliers
  69. Altmetric Badge
    Chapter 68 A Library of Parameterized Floating-Point Modules and Their Use
  70. Altmetric Badge
    Chapter 69 Wordlength as an Architectural Parameter for Reconfigurable Computing Devices
  71. Altmetric Badge
    Chapter 70 An Enhanced POLIS Framework for Fast Exploration and Implementation of I/O Subsystems on CSoC Platforms
  72. Altmetric Badge
    Chapter 71 Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream
  73. Altmetric Badge
    Chapter 72 Efficient Metacomputation Using Self-Reconfiguration
  74. Altmetric Badge
    Chapter 73 An FPGA Co-processor for Real-Time Visual Tracking
  75. Altmetric Badge
    Chapter 74 Implementation of 3-D Adaptive LUM Smoother in Reconfigurable Hardware
  76. Altmetric Badge
    Chapter 75 Custom Coprocessor Based Matrix Algorithms for Image and Signal Processing
  77. Altmetric Badge
    Chapter 76 Parallel FPGA Implementation of the Split and Merge Discrete Wavelet Transform
  78. Altmetric Badge
    Chapter 77 Fully Parameterizable Elliptic Curve Cryptography Processor over GF(2 m )
  79. Altmetric Badge
    Chapter 78 6.78 Gigabits per Second Implementation of the IDEA Cryptographic Algorithm
  80. Altmetric Badge
    Chapter 79 Rijndael Cryptographic Engine on the UltraSONIC Reconfigurable Platform
  81. Altmetric Badge
    Chapter 80 A Cryptanalytic Time-Memory Tradeoff: First FPGA Implementation
  82. Altmetric Badge
    Chapter 81 Creating a World of Smart Re-configurable Devices
  83. Altmetric Badge
    Chapter 82 Interconnection Networks Enable Fine-Grain Dynamic Multi-tasking on FPGAs
  84. Altmetric Badge
    Chapter 83 Multitasking Hardware on the SLAAC1-V Reconfigurable Computing System
  85. Altmetric Badge
    Chapter 84 The Case for Fine-Grained Re-configurable Architectures: An Analysis of Conceived Performance
  86. Altmetric Badge
    Chapter 85 An FPGA Implementation of a Multi-comparand Multi-search Associative Processor
  87. Altmetric Badge
    Chapter 86 AES Implementation on FPGA: Time - Flexibility Tradeoff
  88. Altmetric Badge
    Chapter 87 An FPGA Implementation of the Linear Cryptanalysis
  89. Altmetric Badge
    Chapter 88 Compiling Application-Specific Hardware
  90. Altmetric Badge
    Chapter 89 XPP-VC: A C Compiler with Temporal Partitioning for the PACT-XPP Architecture
  91. Altmetric Badge
    Chapter 90 Sea Cucumber: A Synthesizing Compiler for FPGAs
  92. Altmetric Badge
    Chapter 91 Practical Considerations in the Synthesis of High Performance Digital Filters for Implementation on FPGAs
  93. Altmetric Badge
    Chapter 92 Low Power High Speed Algebraic Integer Frequency Sampling Filters Using FPLDs
  94. Altmetric Badge
    Chapter 93 High Performance Quadrature Digital Mixers for FPGAs
  95. Altmetric Badge
    Chapter 94 HAGAR: Efficient Multi-context Graph Processors
  96. Altmetric Badge
    Chapter 95 Scalable Implementation of the Discrete Element Method on a Reconfigurable Computing Platform
  97. Altmetric Badge
    Chapter 96 On Computing Transitive-Closure Equivalence Sets Using a Hybrid GA-DP Approach
  98. Altmetric Badge
    Chapter 97 REFLIX: A Processor Core for Reactive Embedded Applications
  99. Altmetric Badge
    Chapter 98 Factors Influencing the Performance of a CPU-RFU Hybrid Architecture
  100. Altmetric Badge
    Chapter 99 Implementing Converters in FPLD
  101. Altmetric Badge
    Chapter 100 A Quantitative Understanding of the Performance of Reconfigurable Coprocessors
  102. Altmetric Badge
    Chapter 101 Integration of Reconfigurable Hardware into System-Level Design
  103. Altmetric Badge
    Chapter 102 A Retargetable Macro Generation Method for the Evaluation of Repetitive Configurable Architectures
  104. Altmetric Badge
    Chapter 103 The Integration of SystemC and Hardware-Assisted Verification
  105. Altmetric Badge
    Chapter 104 Using Design Hierarchy to Improve Quality of Results in FPGAs
  106. Altmetric Badge
    Chapter 105 Architecture Design of a Reconfigurable Multiplier for Flexible Coarse-Grain Implementations
  107. Altmetric Badge
    Chapter 106 A General Hardware Design Model for Multicontext FPGAs
  108. Altmetric Badge
    Chapter 107 Dynamically Reconfigurable Hardware — A New Perspective for Neural Network Implementations
  109. Altmetric Badge
    Chapter 108 A Compilation Framework for a Dynamically Reconfigurable Architecture
  110. Altmetric Badge
    Chapter 109 Data Dependent Circuit for Subgraph Isomorphism Problem
  111. Altmetric Badge
    Chapter 110 Exploration of Design Space in ECDSA
  112. Altmetric Badge
    Chapter 111 2D and 3D Computer Graphics Algorithms under MORPHOSYS
  113. Altmetric Badge
    Chapter 112 A HIPERLAN/2 — IEEE 802.11a Reconfigurable System-on-Chip
  114. Altmetric Badge
    Chapter 113 SoftTOTEM: An FPGA Implementation of the TOTEM Parallel Processor
  115. Altmetric Badge
    Chapter 114 Real-Time Medical Diagnosis on a Multiple FPGA-based System
  116. Altmetric Badge
    Chapter 115 Threshold Element-Based Symmetric Function Generators and Their Functional Extension
  117. Altmetric Badge
    Chapter 116 Hardware Implementation of a Multiuser Detection Scheme Based on Recurrent Neural Networks
  118. Altmetric Badge
    Chapter 117 Building Custom FIR Filters Using System Generator
  119. Altmetric Badge
    Chapter 118 SoC Based Low Cost Design of Digital Audio Broadcasting Transport Network Applications
  120. Altmetric Badge
    Chapter 119 Dynamic Constant Coefficient Convolvers Implemented in FPGAs
  121. Altmetric Badge
    Chapter 120 VIZARD II: An FPGA-based Interactive Volume Rendering System
  122. Altmetric Badge
    Chapter 121 RHiNET/NI: A Reconfigurable Network Interface for Cluster Computing
  123. Altmetric Badge
    Chapter 122 General Purpose Prototyping Platform for Data-Processor Research and Development
  124. Altmetric Badge
    Chapter 123 High Speed Computation of Three Dimensional Cellular Automata with FPGA
  125. Altmetric Badge
    Chapter 124 SOPC-based Embedded Smart Strain Gage Sensor
  126. Altmetric Badge
    Chapter 125 Adding Hardware Support to the HotSpot Virtual Machine for Domain Specific Applications
  127. Altmetric Badge
    Chapter 126 An FPGA-based Node Controller for a High Capacity WDM Optical Packet Network
  128. Altmetric Badge
    Chapter 127 FPGA and Mixed FPGA-DSP Implementations of Electrical Drive Algorithms
  129. Altmetric Badge
    Chapter 128 Image Registration of Real-Time Broadcast Video Using the UltraSONIC Reconfigurable Computer
  130. Altmetric Badge
    Chapter 129 A Novel Watermarking Technique for LUT Based FPGA Designs
  131. Altmetric Badge
    Chapter 130 Implementing CSAT Local Search on FPGAs
  132. Altmetric Badge
    Chapter 131 A Reconfigurable Processor Architecture
  133. Altmetric Badge
    Chapter 132 A Reconfigurable System-on-Chip-Based Fast EDM Process Monitor
  134. Altmetric Badge
    Chapter 133 Gene Matching Using JBits
  135. Altmetric Badge
    Chapter 134 Massively Parallel/Reconfigurable Emulation Model for the D-algorithm
  136. Altmetric Badge
    Chapter 135 A Placement/Routing Approach for FPGA Accelerators
Attention for Chapter 44: Fast SiGe HBT BiCMOS FPGAs with New Architecture and Power Saving Techniques
Altmetric Badge

Citations

dimensions_citation
6 Dimensions
You are seeing a free-to-access but limited selection of the activity Altmetric has collected about this research output. Click here to find out more.
Chapter title
Fast SiGe HBT BiCMOS FPGAs with New Architecture and Power Saving Techniques
Chapter number 44
Book title
Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream
Published by
Springer, Berlin, Heidelberg, September 2002
DOI 10.1007/3-540-46117-5_44
Book ISBNs
978-3-54-044108-3, 978-3-54-046117-3
Authors

Kuan Zhou, Channakeshav, Jong-Ru Guo, Chao You, Bryan S. Goda, Russell P. Kraft, John F. McDonald