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Advances in Computer Systems Architecture

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Cover of 'Advances in Computer Systems Architecture'

Table of Contents

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    Book Overview
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    Chapter 1 The Era of Multi-core Chips -A Fresh Look on Software Challenges
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    Chapter 2 Streaming Networks for Coordinating Data-Parallel Programs (Position Statement)
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    Chapter 3 Implementations of Square-Root and Exponential Functions for Large FPGAs
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    Chapter 4 Using Branch Prediction Information for Near-Optimal I-Cache Leakage
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    Chapter 5 Scientific Computing Applications on the Imagine Stream Processor
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    Chapter 6 Enhancing Last-Level Cache Performance by Block Bypassing and Early Miss Determination
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    Chapter 7 A Study of the Performance Potential for Dynamic Instruction Hints Selection
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    Chapter 8 Reorganizing UNIX for Reliability
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    Chapter 9 Critical-Task Anticipation Scheduling Algorithm for Heterogeneous and Grid Computing
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    Chapter 10 Processor Directed Dynamic Page Policy
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    Chapter 11 Static WCET Analysis Based Compiler-Directed DVS Energy Optimization in Real-Time Applications
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    Chapter 12 A Study on Transformation of Self-similar Processes with Arbitrary Marginal Distributions
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    Chapter 13 μ TC – An Intermediate Language for Programming Chip Multiprocessors
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    Chapter 14 Functional Unit Chaining: A Runtime Adaptive Architecture for Reducing Bypass Delays
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    Chapter 15 Trace-Based Data Cache Leakage Reduction at Link Time
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    Chapter 16 Parallelizing User-Defined and Implicit Reductions Globally on Multiprocessors
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    Chapter 17 Overload Protection for Commodity Network Appliances
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    Chapter 18 An Integrated Temporal Partitioning and Mapping Framework for Handling Custom Instructions on a Reconfigurable Functional Unit
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    Chapter 19 A High Performance Simulator System for a Multiprocessor System Based on a Multi-way Cluster
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    Chapter 20 Hardware Budget and Runtime System for Data-Driven Multithreaded Chip Multiprocessor
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    Chapter 21 Combining Wireless Sensor Network with Grid for Intelligent City Traffic
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    Chapter 22 A Novel Processor Architecture for Real-Time Control
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    Chapter 23 A 0-1 Integer Linear Programming Based Approach for Global Locality Optimizations
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    Chapter 24 Design and Analysis of Low Power Image Filters Toward Defect-Resilient Embedded Memories for Multimedia SoCs
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    Chapter 25 Entropy Throttling: A Physical Approach for Maximizing Packet Mobility in Interconnection Networks
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    Chapter 26 Design of an Efficient Flexible Architecture for Color Image Enhancement
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    Chapter 27 Hypercube Communications on Optical Chordal Ring Networks with Chord Length of Three
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    Chapter 28 PMPS(3): A Performance Model of Parallel Systems
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    Chapter 29 Issues and Support for Dynamic Register Allocation
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    Chapter 30 A Heterogeneous Multi-core Processor Architecture for High Performance Computing
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    Chapter 31 Reducing the Branch Power Cost in Embedded Processors Through Static Scheduling, Profiling and SuperBlock Formation
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    Chapter 32 Fault-Free Pairwise Independent Hamiltonian Paths on Faulty Hypercubes
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    Chapter 33 Constructing Node-Disjoint Paths in Enhanced Pyramid Networks
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    Chapter 34 Striping Cache: A Global Cache for Striped Network File System
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    Chapter 35 DTuplesHPC: Distributed Tuple Space for Desktop High Performance Computing
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    Chapter 36 The Algorithm and Circuit Design of a 400MHz 16-Bit Hybrid Multiplier
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    Chapter 37 Live Range Aware Cache Architecture
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    Chapter 38 The Challenges of Efficient Code-Generation for Massively Parallel Architectures
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    Chapter 39 Reliable Systolic Computing Through Redundancy
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    Chapter 40 A Diversity-Controllable Genetic Algorithm for Optimal Fused Traffic Planning on Sensor Networks
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    Chapter 41 A Context-Switch Reduction Heuristic for Power-Aware Off-Line Scheduling
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    Chapter 42 On the Reliability of Drowsy Instruction Caches
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    Chapter 43 Design of a Reconfigurable Cryptographic Engine
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    Chapter 44 Enhancing ICOUNT2.8 Fetch Policy with Better Fairness for SMT Processors
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    Chapter 45 The New BCD Subtractor and Its Reversible Logic Implementation
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    Chapter 46 Power-Efficient Microkernel of Embedded Operating System on Chip
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    Chapter 47 Understanding Prediction Limits Through Unbiased Branches
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    Chapter 48 Bandwidth Optimization of the EMCI for a High Performance 32-bit DSP
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    Chapter 49 Research on Petersen Graphs and Hyper-cubes Connected Interconnection Networks
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    Chapter 50 Cycle Period Analysis and Optimization of Timed Circuits
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    Chapter 51 Acceleration Techniques for Chip-Multiprocessor Simulator Debug
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    Chapter 52 A DDL–Based Software Architecture Model
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    Chapter 53 Branch Behavior Characterization for Multimedia Applications
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    Chapter 54 Optimization and Evaluating of StreamYGX2 on MASA Stream Processor
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    Chapter 55 SecureTorrent: A Security Framework for File Swarming
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    Chapter 56 Register Allocation on Stream Processor with Local Register File
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    Chapter 57 A Self-reconfigurable System-on-Chip Architecture for Satellite On-Board Computer Maintenance
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    Chapter 58 Compile-Time Thread Distinguishment Algorithm on VIM-Based Architecture
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    Chapter 59 Designing a Coarse-Grained Reconfigurable Architecture Using Loop Self-Pipelining
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    Chapter 60 Low-Power Data Cache Architecture by Address Range Reconfiguration for Multimedia Applications
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    Chapter 61 Automatic Synthesis of Interface Circuits from Simplified IP Interface Protocols
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    Chapter 62 An Architectural Leakage Power Reduction Method for Instruction Cache in Ultra Deep Submicron Microprocessors
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    Chapter 63 An Efficient Approach to Energy Saving in Microcontrollers
Attention for Chapter 63: An Efficient Approach to Energy Saving in Microcontrollers
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Chapter title
An Efficient Approach to Energy Saving in Microcontrollers
Chapter number 63
Book title
Advances in Computer Systems Architecture
Published by
Springer, Berlin, Heidelberg, September 2006
DOI 10.1007/11859802_63
Book ISBNs
978-3-54-040056-1, 978-3-54-040058-5
Authors

Wenhong Zhao, Feng Xia

Mendeley readers

The data shown below were compiled from readership statistics for 2 Mendeley readers of this research output. Click here to see the associated Mendeley record.

Geographical breakdown

Country Count As %
Unknown 2 100%

Demographic breakdown

Readers by professional status Count As %
Unknown 2 100%
Readers by discipline Count As %
Unknown 2 100%