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Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation

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Cover of 'Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation'

Table of Contents

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    Book Overview
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    Chapter 1 Constraints, Hurdles and Opportunities for a Successful European Take-Up Action
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    Chapter 2 Architectural Design Space Exploration Achieved through Innovative RTL Power Estimation Techniques
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    Chapter 3 Power Models for Semi-autonomous RTL Macros
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    Chapter 4 Power Macro-Modelling for Firm-Macro
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    Chapter 5 RTL Estimation of Steering Logic Power
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    Chapter 6 Reducing Power Consumption through Dynamic Frequency Scaling for a Class of Digital Receivers
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    Chapter 7 Framework for High-Level Power Estimation of Signal Processing Architectures
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    Chapter 8 Adaptive Bus Encoding Technique for Switching Activity Reduced Data Transfer over Wide System Buses
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    Chapter 9 Accurate Power Estimation of Logic Structures Based on Timed Boolean Functions
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    Chapter 10 A Holistic Approach to System Level Energy Optimization
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    Chapter 11 Early Power Estimation for System-on-Chip Designs
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    Chapter 12 Design-Space Exploration of Low Power Coarse Grained Reconfigurable Datapath Array Architectures
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    Chapter 13 Internal Power Dissipation Modeling and Minimization for Submicronic CMOS Design
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    Chapter 14 Impact of Voltage Scaling on Glitch Power Consumption
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    Chapter 15 Degradation Delay Model Extension to CMOS Gates
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    Chapter 16 Second Generation Delay Model for Submicron CMOS Process
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    Chapter 17 Semi-modular Latch Chains for Asynchronous Circuit Design
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    Chapter 18 Asynchronous First-in First-out Queues
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    Chapter 19 Comparative Study on Self-Checking Carry-Propagate Adders in Terms of Area, Power and Performance
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    Chapter 20 VLSI Implementation of a Low-Power High-Speed Self-Timed Adder
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    Chapter 21 Low Power Design Techniques for Contactless Chipcards
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    Chapter 22 Dynamic Memory Design for Low Data-Retention Power
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    Chapter 23 Double-Latch Clocking Scheme for Low-Power I.P. Cores
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    Chapter 24 Architecture, Design, and Verification of an 18 Million Transistor Digital Television and Media Processor Chip
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    Chapter 25 Cost-Efficient C-Level Design of an MPEG-4 Video Decoder
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    Chapter 26 Data-Reuse and Parallel Embedded Architectures for Low-Power, Real-Time Multimedia Applications
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    Chapter 27 Design of Reversible Logic Circuits by Means of Control Gates
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    Chapter 28 Modeling of Power Consumption of Adiabatic Gates versus Fan in and Comparison with Conventional Gates
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    Chapter 29 An Adiabatic Multiplier
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    Chapter 30 Logarithmic Number System for Low-Power Arithmetic
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    Chapter 31 An Application of Self-Timed Circuits to the Reduction of Switching Noise in Analog-Digital Circuits
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    Chapter 32 PARCOURS — Substrate Crosstalk Analysis for Complex Mixed-Signal-Circuits
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    Chapter 33 Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits
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    Chapter 34 Computer Aided Generation of Analytic Models for Nonlinear Function Blocks
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Title
Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation
Published by
Springer, June 2003
DOI 10.1007/3-540-45373-3
ISBNs
978-3-54-045373-4, 978-3-54-041068-3
Editors

Soudris, Dimitrios, Pirsch, Peter, Barke, Erich