Embedded Computer Systems: Architectures, Modeling, and Simulation

Table of Contents

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   Book Overview
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   Chapter 1 What Else Is Broken? Can We Fix It?
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   Chapter 2 Programmable and Scalable Architecture for Graphics Processing Units
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   Chapter 3 The Abstract Streaming Machine: Compile-Time Performance Modelling of Stream Programs on Heterogeneous Multiprocessors
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   Chapter 4 CABAC Accelerator Architectures for Video Compression in Future Multimedia: A Survey
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   Chapter 5 Programmable Accelerators for Reconfigurable Video Decoder
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   Chapter 6 Scenario Based Mapping of Dynamic Applications on MPSoC: A 3D Graphics Case Study
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   Chapter 7 Multiple Description Scalable Coding for Video Transmission over Unreliable Networks
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   Chapter 8 Evaluation of Different Multithreaded and Multicore Processor Configurations for SoPC
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    Chapter 9 Implementing Fine/Medium Grained TLP Support in a Many-Core Architecture
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    Chapter 10 Implementation of W-CDMA Cell Search on a FPGA Based Multi-Processor System-on-Chip with Power Management
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    Chapter 11 A Multiprocessor Architecture with an Omega Network for the Massively Parallel Model GCA
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    Chapter 12 Towards Automated FSMD Partitioning for Low Power Using Simulated Annealing
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    Chapter 13 Radix-4 Recoded Multiplier on Quantum-Dot Cellular Automata
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    Chapter 14 Prediction in Dynamic SDRAM Controller Policies
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    Chapter 15 Inversion/Non-inversion Implementation for an 11,424 Gate-Count Dynamic Optically Reconfigurable Gate Array VLSI
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    Chapter 16 Visualization of Computer Architecture Simulation Data for System-Level Design Space Exploration
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    Chapter 17 Modeling Scalable SIMD DSPs in LISA
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    Chapter 18 NoGAP: A Micro Architecture Construction Framework
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    Chapter 19 A Comparison of NoTA and GENESYS
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    Chapter 20 Introduction to Instruction-Set Customization
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    Chapter 21 Constraint-Driven Identification of Application Specific Instructions in the DURASE System
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    Chapter 22 A Generic Design Flow for Application Specific Processor Customization through Instruction-Set Extensions (ISEs)
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    Chapter 23 Runtime Adaptive Extensible Embedded Processors — A Survey
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    Chapter 24 Introduction to the Future of Reconfigurable Computing and Processor Architectures
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    Chapter 25 An Embrace-and-Extend Approach to Managing the Complexity of Future Heterogeneous Systems
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    Chapter 26 Applying the Stream-Based Computing Model to Design Hardware Accelerators: A Case Study
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    Chapter 27 Reconfigurable Multicore Server Processors for Low Power Operation
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    Chapter 28 Reconfigurable Computing in the New Age of Parallelism
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    Chapter 29 Reconfigurable Multithreading Architectures: A Survey
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    Chapter 30 Introduction to Mastering Cell BE and GPU Execution Platforms
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    Chapter 31 Efficient Mapping of Multiresolution Image Filtering Algorithms on Graphics Processors
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    Chapter 32 Implementing Blocked Sparse Matrix-Vector Multiplication on NVIDIA GPUs
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    Chapter 33 Experiences with Cell-BE and GPU for Tomography
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    Chapter 34 Realizing FIFO Communication When Mapping Kahn Process Networks onto the Cell
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    Chapter 35 Exploiting Locality on the Cell/B.E. through Bypassing
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    Chapter 36 Exploiting the Cell/BE Architecture with the StarPU Unified Runtime System