↓ Skip to main content

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation

Overview of attention for book
Cover of 'Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation'

Table of Contents

  1. Altmetric Badge
    Book Overview
  2. Altmetric Badge
    Chapter 1 A Power-Efficient and Scalable Load-Store Queue Design
  3. Altmetric Badge
    Chapter 2 Power Consumption Reduction Using Dynamic Control of Micro Processor Performance
  4. Altmetric Badge
    Chapter 3 Low Power Techniques Applied to a 80C51 Microcontroller for High Temperature Applications
  5. Altmetric Badge
    Chapter 4 Dynamic Instruction Cascading on GALS Microprocessors
  6. Altmetric Badge
    Chapter 5 Power Reduction of Superscalar Processor Functional Units by Resizing Adder-Width
  7. Altmetric Badge
    Chapter 6 A Retargetable Environment for Power-Aware Code Evaluation: An Approach Based on Coloured Petri Net
  8. Altmetric Badge
    Chapter 7 Designing Low-Power Embedded Software for Mass-Produced Microprocessor by Using a Loop Table in On-Chip Memory
  9. Altmetric Badge
    Chapter 8 Energy Characterization of Garbage Collectors for Dynamic Applications on Embedded Systems
  10. Altmetric Badge
    Chapter 9 Optimizing the Configuration of Dynamic Voltage Scaling Points in Real-Time Applications
  11. Altmetric Badge
    Chapter 10 Systematic Preprocessing of Data Dependent Constructs for Embedded Systems
  12. Altmetric Badge
    Chapter 11 Temperature Aware Datapath Scheduling
  13. Altmetric Badge
    Chapter 12 Memory Hierarchy Energy Cost of a Direct Filtering Implementation of the Wavelet Transform
  14. Altmetric Badge
    Chapter 13 Improving the Memory Bandwidth Utilization Using Loop Transformations
  15. Altmetric Badge
    Chapter 14 Power-Aware Scheduling for Hard Real-Time Embedded Systems Using Voltage-Scaling Enabled Architectures
  16. Altmetric Badge
    Chapter 15 Design of Digital Filters for Low Power Applications Using Integer Quadratic Programming
  17. Altmetric Badge
    Chapter 16 A High Level Constant Coefficient Multiplier Power Model for Power Estimation on High Levels of Abstraction
  18. Altmetric Badge
    Chapter 17 An Energy-Tree Based Routing Algorithm in Wireless Ad-Hoc Network Environments
  19. Altmetric Badge
    Chapter 18 Energy-Aware System-on-Chip for 5 GHz Wireless LANs
  20. Altmetric Badge
    Chapter 19 Low-Power VLSI Architectures for OFDM Transmitters Based on PAPR Reduction
  21. Altmetric Badge
    Chapter 20 An Activity Monitor for Power/Performance Tuning of CMOS Digital Circuits
  22. Altmetric Badge
    Chapter 21 Power Management for Low-Power Battery Operated Portable Systems Using Current-Mode Techniques
  23. Altmetric Badge
    Chapter 22 Power Consumption in Reversible Logic Addressed by a Ramp Voltage
  24. Altmetric Badge
    Chapter 23 Leakage and Dynamic Glitch Power Minimization Using Integer Linear Programming for V th Assignment and Path Balancing
  25. Altmetric Badge
    Chapter 24 Back Annotation in High Speed Asynchronous Design
  26. Altmetric Badge
    Chapter 25 Optimization of Reliability and Power Consumption in Systems on a Chip
  27. Altmetric Badge
    Chapter 26 Performance Gains from Partitioning Embedded Applications in Processor-FPGA SoCs
  28. Altmetric Badge
    Chapter 27 A Thermal Aware Floorplanning Algorithm Supporting Voltage Islands for Low Power SOC Design
  29. Altmetric Badge
    Chapter 28 Power Supply Selective Mapping for Accurate Timing Analysis
  30. Altmetric Badge
    Chapter 29 Switching Sensitive Driver Circuit to Combat Dynamic Delay in On-Chip Buses
  31. Altmetric Badge
    Chapter 30 PSK Signalling on NoC Buses
  32. Altmetric Badge
    Chapter 31 Exploiting Cross-Channel Correlation for Energy-Efficient LCD Bus Encoding
  33. Altmetric Badge
    Chapter 32 Closed-Form Bounds for Interconnect-Aware Minimum-Delay Gate Sizing
  34. Altmetric Badge
    Chapter 33 Efficient Simulation of Power/Ground Networks with Package and Vias
  35. Altmetric Badge
    Chapter 34 Output Resistance Scaling Model for Deep-Submicron Cmos Buffers for Timing Performance Optimisation
  36. Altmetric Badge
    Chapter 35 Application of Internode Model to Global Power Consumption Estimation in SCMOS Gates
  37. Altmetric Badge
    Chapter 36 Compact Static Power Model of Complex CMOS Gates
  38. Altmetric Badge
    Chapter 37 Energy Consumption in RC Tree Circuits with Exponential Inputs: An Analytical Model
  39. Altmetric Badge
    Chapter 38 Statistical Critical Path Analysis Considering Correlations
  40. Altmetric Badge
    Chapter 39 A CAD Platform for Sensor Interfaces in Low-Power Applications
  41. Altmetric Badge
    Chapter 40 An Integrated Environment for Embedded Hard Real-Time Systems Scheduling with Timing and Energy Constraints
  42. Altmetric Badge
    Chapter 41 Efficient Post-layout Power-Delay Curve Generation
  43. Altmetric Badge
    Chapter 42 Power – Performance Optimization for Custom Digital Circuits
  44. Altmetric Badge
    Chapter 43 Switching-Activity Directed Clustering Algorithm for Low Net-Power Implementation of FPGAs
  45. Altmetric Badge
    Chapter 44 Logic-Level Fast Current Simulation for Digital CMOS Circuits
  46. Altmetric Badge
    Chapter 45 Design of Variable Input Delay Gates for Low Dynamic Power Circuits
  47. Altmetric Badge
    Chapter 46 Two-Phase Clocking and a New Latch Design for Low-Power Portable Applications
  48. Altmetric Badge
    Chapter 47 Power Dissipation Reduction During Synthesis of Two-Level Logic Based on Probability of Input Vectors Changes
  49. Altmetric Badge
    Chapter 48 Energy-Efficient Value-Based Selective Refresh for Embedded DRAMs
  50. Altmetric Badge
    Chapter 49 Design and Implementation of a Memory Generator for Low-Energy Application-Specific Block-Enabled SRAMs
  51. Altmetric Badge
    Chapter 50 Static Noise Margin Analysis of Sub-threshold SRAM Cells in Deep Sub-micron Technology
  52. Altmetric Badge
    Chapter 51 An Adaptive Technique for Reducing Leakage and Dynamic Power in Register Files and Reorder Buffers
  53. Altmetric Badge
    Chapter 52 Parameter Variation Effects on Timing Characteristics of High Performance Clocked Registers
  54. Altmetric Badge
    Chapter 53 Low-Power Aspects of Nonlinear Signal Processing
  55. Altmetric Badge
    Chapter 54 Reducing Energy Consumption of Computer Display by Camera-Based User Monitoring
  56. Altmetric Badge
    Chapter 55 Controlling Peak Power Consumption During Scan Testing: Power-Aware DfT and Test Set Perspectives
  57. Altmetric Badge
    Chapter 56 A Design Methodology for Secured ICs Using Dynamic Current Mode Logic
  58. Altmetric Badge
    Chapter 57 Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
  59. Altmetric Badge
    Chapter 58 A Method to Design Compact Dual-rail Asynchronous Primitives
  60. Altmetric Badge
    Chapter 59 Enhanced GALS Techniques for Datapath Applications
  61. Altmetric Badge
    Chapter 60 Optimizing SHA-1 Hash Function for High Throughput with a Partial Unrolling Study
  62. Altmetric Badge
    Chapter 61 Area-Aware Pipeline Gating for Embedded Processors
  63. Altmetric Badge
    Chapter 62 Fast Low-Power 64-Bit Modular Hybrid Adder
  64. Altmetric Badge
    Chapter 63 Speed Indicators for Circuit Optimization
  65. Altmetric Badge
    Chapter 64 Synthesis of Hybrid CBL/CMOS Cell Using Multiobjective Evolutionary Algorithms
  66. Altmetric Badge
    Chapter 65 Power-Clock Gating in Adiabatic Logic Circuits
  67. Altmetric Badge
    Chapter 66 Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
  68. Altmetric Badge
    Chapter 67 Efficient Clock Distribution Scheme for VLSI RNS-Enabled Controllers
  69. Altmetric Badge
    Chapter 68 Power Dissipation Impact of the Technology Mapping Synthesis on Look-Up Table Architectures
  70. Altmetric Badge
    Chapter 69 The Optimal Wire Order for Low Power CMOS
  71. Altmetric Badge
    Chapter 70 Effect of Post-oxidation Annealing on the Electrical Properties of Anodic Oxidized Films in Pure Water
  72. Altmetric Badge
    Chapter 71 Temperature Dependency in UDSM Process
  73. Altmetric Badge
    Chapter 72 Circuit Design Techniques for On-Chip Power Supply Noise Monitoring System
  74. Altmetric Badge
    Chapter 73 A Novel Approach to the Design of a Linearized Widely Tunable Very Low Power and Low Noise Differential Transconductor
  75. Altmetric Badge
    Chapter 74 A New Model for Timing Jitter Caused by Device Noise in Current-Mode Logic Frequency Dividers
  76. Altmetric Badge
    Chapter 75 Digital Hearing Aids: Challenges and Solutions for Ultra Low Power
  77. Altmetric Badge
    Chapter 76 Tutorial Hearing Aid Algorithms
  78. Altmetric Badge
    Chapter 77 Optimization of Digital Audio Processing Algorithms Suitable for Hearing Aids
  79. Altmetric Badge
    Chapter 78 Optimization of Modules for Digital Audio Processing
  80. Altmetric Badge
    Chapter 79 Traveling the Wild Frontier of Ultra Low-Power Design
  81. Altmetric Badge
    Chapter 80 DLV (Deep Low Voltage): Circuits and Devices
  82. Altmetric Badge
    Chapter 81 Wireless Sensor Networks: A New Life Paradigm
  83. Altmetric Badge
    Chapter 82 Cryptography: Circuits and Systems Approach
Overall attention for this book and its chapters
Altmetric Badge

Mentioned by

news
1 news outlet
patent
1 patent
googleplus
1 Google+ user

Citations

dimensions_citation
1 Dimensions

Readers on

mendeley
3 Mendeley
You are seeing a free-to-access but limited selection of the activity Altmetric has collected about this research output. Click here to find out more.
Title
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Published by
Springer, Berlin, Heidelberg, January 2005
DOI 10.1007/11556930
ISBNs
978-3-54-029013-1, 978-3-54-032080-7
Editors

Vassilis Paliouras, Johan Vounckx, Diederik Verkest

Mendeley readers

The data shown below were compiled from readership statistics for 3 Mendeley readers of this research output. Click here to see the associated Mendeley record.

Geographical breakdown

Country Count As %
Iraq 1 33%
Unknown 2 67%

Demographic breakdown

Readers by professional status Count As %
Student > Ph. D. Student 2 67%
Student > Master 1 33%
Student > Bachelor 1 33%
Lecturer 1 33%
Researcher 1 33%
Other 0 0%
Readers by discipline Count As %
Engineering 3 100%
Computer Science 2 67%
Agricultural and Biological Sciences 1 33%