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Mendeley readers
Chapter title |
Design of Variable Input Delay Gates for Low Dynamic Power Circuits
|
---|---|
Chapter number | 45 |
Book title |
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
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Published by |
Springer, Berlin, Heidelberg, September 2005
|
DOI | 10.1007/11556930_45 |
Book ISBNs |
978-3-54-029013-1, 978-3-54-032080-7
|
Authors |
Tezaswi Raja, Vishwani D. Agrawal, Michael Bushnell |
Mendeley readers
The data shown below were compiled from readership statistics for 2 Mendeley readers of this research output. Click here to see the associated Mendeley record.
Geographical breakdown
Country | Count | As % |
---|---|---|
Unknown | 2 | 100% |
Demographic breakdown
Readers by professional status | Count | As % |
---|---|---|
Student > Ph. D. Student | 2 | 100% |
Student > Doctoral Student | 1 | 50% |
Readers by discipline | Count | As % |
---|---|---|
Mathematics | 1 | 50% |
Computer Science | 1 | 50% |
Engineering | 1 | 50% |