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Reconfigurable Computing: Architectures, Tools and Applications

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Cover of 'Reconfigurable Computing: Architectures, Tools and Applications'

Table of Contents

  1. Altmetric Badge
    Book Overview
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    Chapter 1 High-Performance Energy-Efficient Reconfigurable Accelerators/Co-processors for Tera-Scale Multi-core Microprocessors
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    Chapter 2 Process Variability and Degradation: New Frontier for Reconfigurable
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    Chapter 3 Towards Analytical Methods for FPGA Architecture Investigation
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    Chapter 4 Generic Systolic Array for Run-Time Scalable Cores
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    Chapter 5 Virtualization within a Parallel Array of Homogeneous Processing Units
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    Chapter 6 Feasibility Study of a Self-healing Hardware Platform
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    Chapter 7 Application-Specific Signatures for Transactional Memory in Soft Processors
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    Chapter 8 Towards Rapid Dynamic Partial Reconfiguration in Video-Based Driver Assistance Systems
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    Chapter 9 Parametric Encryption Hardware Design
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    Chapter 10 A Reconfigurable Implementation of the Tate Pairing Computation over GF (2 m )
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    Chapter 11 Application Specific FPGA Using Heterogeneous Logic Blocks
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    Chapter 12 Reconfigurable Communication Networks in a Parametric SIMD Parallel System on Chip
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    Chapter 13 A Dedicated Reconfigurable Architecture for Finite State Machines
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    Chapter 14 MEMS Dynamic Optically Reconfigurable Gate Array Usable under a Space Radiation Environment
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    Chapter 15 An FPGA Accelerator for Hash Tree Generation in the Merkle Signature Scheme
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    Chapter 16 A Fused Hybrid Floating-Point and Fixed-Point Dot-Product for FPGAs
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    Chapter 17 Optimising Memory Bandwidth Use for Matrix-Vector Multiplication in Iterative Methods
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    Chapter 18 Design of a Financial Application Driven Multivariate Gaussian Random Number Generator for an FPGA
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    Chapter 19 3D Compaction: A Novel Blocking-Aware Algorithm for Online Hardware Task Scheduling and Placement on 2D Partially Reconfigurable Devices
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    Chapter 20 TROUTE: A Reconfigurability-Aware FPGA Router
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    Chapter 21 Space and Time Sharing of Reconfigurable Hardware for Accelerated Parallel Processing
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    Chapter 22 Routing-Aware Application Mapping Considering Steiner Points for Coarse-Grained Reconfigurable Architecture
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    Chapter 23 Design Automation for Reconfigurable Interconnection Networks
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    Chapter 24 A Framework for Enabling Fault Tolerance in Reconfigurable Architectures
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    Chapter 25 QUAD – A Memory Access Pattern Analyser
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    Chapter 26 Hierarchical Loop Partitioning for Rapid Generation of Runtime Configurations
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    Chapter 27 Reconfigurable Computing and Task Scheduling for Active Storage Service Processing
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    Chapter 28 A Reconfigurable Disparity Engine for Stereovision in Advanced Driver Assistance Systems
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    Chapter 29 A Modified Merging Approach for Datapath Configuration Time Reduction
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    Chapter 30 Reconfigurable Computing Education in Computer Science
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    Chapter 31 Hardware Implementation of the Orbital Function for Quantum Chemistry Calculations
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    Chapter 32 Reconfigurable Polyphase Filter Bank Architecture for Spectrum Sensing
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    Chapter 33 Reconfigurable Computing: Architectures, Tools and Applications
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    Chapter 34 A GMM-Based Speaker Identification System on FPGA
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    Chapter 35 An FPGA-Based Real-Time Event Sampler
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    Chapter 36 A Performance Evaluation of CUBE: One-Dimensional 512 FPGA Cluster
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    Chapter 37 An Analysis of Delay Based PUF Implementations on FPGA
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    Chapter 38 Comparison of Bit Serial Computation with Bit Parallel Computation for Reconfigurable Processor
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    Chapter 39 FPGA Implementation of QR Decomposition Using MGS Algorithm
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    Chapter 40 Memory-Centric Communication Architecture for Reconfigurable Computing
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    Chapter 41 Integrated Design Environment for Reconfigurable HPC
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    Chapter 42 Architecture-Aware Custom Instruction Generation for Reconfigurable Processors
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    Chapter 43 Cost and Performance Evaluation of a Noise Filter for Partitioning in Co-design Methodologies
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    Chapter 44 Towards a Tighter Integration of Generated and Custom-Made Hardware
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    Chapter 45 Pipelined Microprocessors Optimization and Debugging
Attention for Chapter 36: A Performance Evaluation of CUBE: One-Dimensional 512 FPGA Cluster
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Chapter title
A Performance Evaluation of CUBE: One-Dimensional 512 FPGA Cluster
Chapter number 36
Book title
Reconfigurable Computing: Architectures, Tools and Applications
Published by
Springer, Berlin, Heidelberg, March 2010
DOI 10.1007/978-3-642-12133-3_36
Book ISBNs
978-3-64-212132-6, 978-3-64-212133-3
Authors

Masato Yoshimi, Yuri Nishikawa, Mitsunori Miki, Tomoyuki Hiroyasu, Hideharu Amano, Oskar Mencer, Yoshimi, Masato, Nishikawa, Yuri, Miki, Mitsunori, Hiroyasu, Tomoyuki, Amano, Hideharu, Mencer, Oskar

Mendeley readers

Mendeley readers

The data shown below were compiled from readership statistics for 3 Mendeley readers of this research output. Click here to see the associated Mendeley record.

Geographical breakdown

Country Count As %
Japan 1 33%
Unknown 2 67%

Demographic breakdown

Readers by professional status Count As %
Student > Ph. D. Student 2 67%
Professor 1 33%
Readers by discipline Count As %
Computer Science 3 100%