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"CMOS Nanophotonics: Technology, System Implications, and a CMP Case Study", HP Labs, Aug 27, 2010 http://t.co/cO7CBE2iQR @ogawa_tter
Low Power Networks-on-Chip
Overview of attention for book
Table of Contents
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Altmetric BadgeBook Overview
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Altmetric BadgeChapter 1 Hybrid Circuit/Packet Switched Network for Energy Efficient on-Chip Interconnections
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Altmetric BadgeChapter 2 Run-Time Power-Gating Techniques for Low-Power On-Chip Networks
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Altmetric BadgeChapter 3 Adaptive Voltage Control for Energy-Efficient NoC Links
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Altmetric BadgeChapter 4 Asynchronous Communications for NoCs
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Altmetric BadgeChapter 5 Application-Specific Routing Algorithms for Low Power Network on Chip Design
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Altmetric BadgeChapter 6 Adaptive Data Compression for Low-Power On-Chip Networks
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Altmetric BadgeChapter 7 Latency-Constrained, Power-Optimized NoC Design for a 4G SoC: A Case Study
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Altmetric BadgeChapter 8 Design and Analysis of NoCs for Low-Power 2D and 3D SoCs
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Altmetric BadgeChapter 9 CMOS Nanophotonics: Technology, System Implications, and a CMP Case Study
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Altmetric BadgeChapter 10 RF-Interconnect for Future Network-On-Chip