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Low Power Networks-on-Chip

Overview of attention for book
Attention for Chapter 2: Run-Time Power-Gating Techniques for Low-Power On-Chip Networks
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Chapter title
Run-Time Power-Gating Techniques for Low-Power On-Chip Networks
Chapter number 2
Book title
Low Power Networks-on-Chip
Published by
Springer, Boston, MA, January 2011
DOI 10.1007/978-1-4419-6911-8_2
Book ISBNs
978-1-4419-6910-1, 978-1-4419-6911-8
Authors

Hiroki Matsutani, Michihiro Koibuchi, Hiroshi Nakamura, Hideharu Amano

Mendeley readers

The data shown below were compiled from readership statistics for 1 Mendeley reader of this research output. Click here to see the associated Mendeley record.

Geographical breakdown

Country Count As %
Unknown 1 100%

Demographic breakdown

Readers by professional status Count As %
Researcher 1 100%
Readers by discipline Count As %
Computer Science 1 100%