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Low Power Networks-on-Chip

Overview of attention for book
Cover of 'Low Power Networks-on-Chip'

Table of Contents

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    Book Overview
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    Chapter 1 Hybrid Circuit/Packet Switched Network for Energy Efficient on-Chip Interconnections
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    Chapter 2 Run-Time Power-Gating Techniques for Low-Power On-Chip Networks
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    Chapter 3 Adaptive Voltage Control for Energy-Efficient NoC Links
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    Chapter 4 Asynchronous Communications for NoCs
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    Chapter 5 Application-Specific Routing Algorithms for Low Power Network on Chip Design
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    Chapter 6 Adaptive Data Compression for Low-Power On-Chip Networks
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    Chapter 7 Latency-Constrained, Power-Optimized NoC Design for a 4G SoC: A Case Study
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    Chapter 8 Design and Analysis of NoCs for Low-Power 2D and 3D SoCs
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    Chapter 9 CMOS Nanophotonics: Technology, System Implications, and a CMP Case Study
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    Chapter 10 RF-Interconnect for Future Network-On-Chip
Attention for Chapter 2: Run-Time Power-Gating Techniques for Low-Power On-Chip Networks
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Citations

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Chapter title
Run-Time Power-Gating Techniques for Low-Power On-Chip Networks
Chapter number 2
Book title
Low Power Networks-on-Chip
Published by
Springer, Boston, MA, January 2011
DOI 10.1007/978-1-4419-6911-8_2
Book ISBNs
978-1-4419-6910-1, 978-1-4419-6911-8
Authors

Hiroki Matsutani, Michihiro Koibuchi, Hiroshi Nakamura, Hideharu Amano

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Mendeley readers

Mendeley readers

The data shown below were compiled from readership statistics for 1 Mendeley reader of this research output. Click here to see the associated Mendeley record.

Geographical breakdown

Country Count As %
Unknown 1 100%

Demographic breakdown

Readers by professional status Count As %
Student > Bachelor 1 100%
Readers by discipline Count As %
Engineering 1 100%

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