↓ Skip to main content

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation

Overview of attention for book
Cover of 'Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation'

Table of Contents

  1. Altmetric Badge
    Book Overview
  2. Altmetric Badge
    Chapter 1 System-Level Application-Specific NoC Design for Network and Multimedia Applications
  3. Altmetric Badge
    Chapter 2 Fast and Accurate Embedded Systems Energy Characterization Using Non-intrusive Measurements
  4. Altmetric Badge
    Chapter 3 A Flexible General-Purpose Parallelizing Architecture for Nested Loops in Reconfigurable Platforms
  5. Altmetric Badge
    Chapter 4 An Automatic Design Flow for Mapping Application onto a 2D Mesh NoC Architecture
  6. Altmetric Badge
    Chapter 5 Template Vertical Dictionary-Based Program Compression Scheme on the TTA
  7. Altmetric Badge
    Chapter 6 Asynchronous Functional Coupling for Low Power Sensor Network Processors
  8. Altmetric Badge
    Chapter 7 A Heuristic for Reducing Dynamic Power Dissipation in Clocked Sequential Designs
  9. Altmetric Badge
    Chapter 8 Low-Power Content Addressable Memory With Read/Write and Matched Mask Ports
  10. Altmetric Badge
    Chapter 9 The Design and Implementation of a Power Efficient Embedded SRAM
  11. Altmetric Badge
    Chapter 10 Design of a Linear Power Amplifier with ±1.5V Power Supply Using ALADIN
  12. Altmetric Badge
    Chapter 11 Settling Time Minimization of Operational Amplifiers
  13. Altmetric Badge
    Chapter 12 Low-Voltage Low-Power Curvature-Corrected Voltage Reference Circuit Using DTMOSTs
  14. Altmetric Badge
    Chapter 13 Computation of Joint Timing Yield of Sequential Networks Considering Process Variations
  15. Altmetric Badge
    Chapter 14 A Simple Statistical Timing Analysis Flow and Its Application to Timing Margin Evaluation
  16. Altmetric Badge
    Chapter 15 A Statistical Approach to the Timing-Yield Optimization of Pipeline Circuits
  17. Altmetric Badge
    Chapter 16 A Novel Gate-Level NBTI Delay Degradation Model with Stacking Effect
  18. Altmetric Badge
    Chapter 17 Modelling the Impact of High Level Leakage Optimization Techniques on the Delay of RT-Components
  19. Altmetric Badge
    Chapter 18 Logic Style Comparison for Ultra Low Power Operation in 65nm Technology
  20. Altmetric Badge
    Chapter 19 Design-In Reliability for 90-65nm CMOS Nodes Submitted to Hot-Carriers and NBTI Degradation
  21. Altmetric Badge
    Chapter 20 Clock Distribution Techniques for Low-EMI Design
  22. Altmetric Badge
    Chapter 21 Crosstalk Waveform Modeling Using Wave Fitting
  23. Altmetric Badge
    Chapter 22 Weakness Identification for Effective Repair of Power Distribution Network
  24. Altmetric Badge
    Chapter 23 New Adaptive Encoding Schemes for Switching Activity Balancing in On-Chip Buses
  25. Altmetric Badge
    Chapter 24 On the Necessity of Combining Coding with Spacing and Shielding for Improving Performance and Power in Very Deep Sub-micron Interconnects
  26. Altmetric Badge
    Chapter 25 Soft Error-Aware Power Optimization Using Gate Sizing
  27. Altmetric Badge
    Chapter 26 Automated Instruction Set Characterization and Power Profile Driven Software Optimization for Mobile Devices
  28. Altmetric Badge
    Chapter 27 RTL Power Modeling and Estimation of Sleep Transistor Based Power Gating
  29. Altmetric Badge
    Chapter 28 Functional Verification of Low Power Designs at RTL
  30. Altmetric Badge
    Chapter 29 XEEMU: An Improved XScale Power Simulator
  31. Altmetric Badge
    Chapter 30 Low Power Elliptic Curve Cryptography
  32. Altmetric Badge
    Chapter 31 Design and Test of Self-checking Asynchronous Control Circuit
  33. Altmetric Badge
    Chapter 32 An Automatic Design Flow for Implementation of Side Channel Attacks Resistant Crypto-Chips
  34. Altmetric Badge
    Chapter 33 Analysis and Improvement of Dual Rail Logic as a Countermeasure Against DPA
  35. Altmetric Badge
    Chapter 34 Performance Optimization of Embedded Applications in a Hybrid Reconfigurable Platform
  36. Altmetric Badge
    Chapter 35 The Energy Scalability of Wavelet-Based, Scalable Video Decoding
  37. Altmetric Badge
    Chapter 36 Direct Memory Access Optimization in Wireless Terminals for Reduced Memory Latency and Energy Consumption
  38. Altmetric Badge
    Chapter 37 Exploiting Input Variations for Energy Reduction
  39. Altmetric Badge
    Chapter 38 A Model of DPA Syndrome and Its Application to the Identification of Leaking Gates
  40. Altmetric Badge
    Chapter 39 Static Power Consumption in CMOS Gates Using Independent Bodies
  41. Altmetric Badge
    Chapter 40 Moderate Inversion: Highlights for Low Voltage Design
  42. Altmetric Badge
    Chapter 41 On Two-Pronged Power-Aware Voltage Scheduling for Multi-processor Real-Time Systems
  43. Altmetric Badge
    Chapter 42 Semi Custom Design: A Case Study on SIMD Shufflers
  44. Altmetric Badge
    Chapter 43 Optimization for Real-Time Systems with Non-convex Power Versus Speed Models
  45. Altmetric Badge
    Chapter 44 Triple-Threshold Static Power Minimization in High-Level Synthesis of VLSI CMOS
  46. Altmetric Badge
    Chapter 45 A Fast and Accurate Power Estimation Methodology for QDI Asynchronous Circuits
  47. Altmetric Badge
    Chapter 46 Subthreshold Leakage Modeling and Estimation of General CMOS Complex Gates
  48. Altmetric Badge
    Chapter 47 A Platform for Mixed HW/SW Algorithm Specifications for the Exploration of SW and HW Partitioning
  49. Altmetric Badge
    Chapter 48 Fast Calculation of Permissible Slowdown Factors for Hard Real-Time Systems
  50. Altmetric Badge
    Chapter 49 Design Methodology and Software Tool for Estimation of Multi-level Instruction Cache Memory Miss Rate
  51. Altmetric Badge
    Chapter 50 A Statistical Model of Logic Gates for Monte Carlo Simulation Including On-Chip Variations
  52. Altmetric Badge
    Chapter 51 Switching Activity Reduction of MAC-Based FIR Filters with Correlated Input Data
  53. Altmetric Badge
    Chapter 52 Performance of CMOS and Floating-Gate Full-Adders Circuits at Subthreshold Power Supply
  54. Altmetric Badge
    Chapter 53 Low-Power Digital Filtering Based on the Logarithmic Number System
  55. Altmetric Badge
    Chapter 54 A Power Supply Selector for Energy- and Area-Efficient Local Dynamic Voltage Scaling
  56. Altmetric Badge
    Chapter 55 Dependability Evaluation of Time-Redundancy Techniques in Integer Multipliers
  57. Altmetric Badge
    Chapter 56 Design and Industrialization Challenges of Memory Dominated SOCs
  58. Altmetric Badge
    Chapter 57 Statistical Static Timing Analysis: A New Approach to Deal with Increased Process Variability in Advanced Nanometer Technologies
  59. Altmetric Badge
    Chapter 58 Analog Power Modelling
  60. Altmetric Badge
    Chapter 59 Technological Trends, Design Constraints and Design Implementation Challenges in Mobile Phone Platforms
  61. Altmetric Badge
    Chapter 60 System Design from Instrument Level Down to ASIC Transistors with Speed and Low Power as Driving Parameters
Attention for Chapter 28: Functional Verification of Low Power Designs at RTL
Altmetric Badge

Mentioned by

patent
1 patent

Citations

dimensions_citation
4 Dimensions

Readers on

mendeley
2 Mendeley
You are seeing a free-to-access but limited selection of the activity Altmetric has collected about this research output. Click here to find out more.
Chapter title
Functional Verification of Low Power Designs at RTL
Chapter number 28
Book title
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Published by
Springer, Berlin, Heidelberg, September 2007
DOI 10.1007/978-3-540-74442-9_28
Book ISBNs
978-3-54-074441-2, 978-3-54-074442-9
Authors

Allan Crone, Gabriel Chidolue

Mendeley readers

Mendeley readers

The data shown below were compiled from readership statistics for 2 Mendeley readers of this research output. Click here to see the associated Mendeley record.

Geographical breakdown

Country Count As %
Unknown 2 100%

Demographic breakdown

Readers by professional status Count As %
Student > Ph. D. Student 1 50%
Student > Bachelor 1 50%
Student > Postgraduate 1 50%
Readers by discipline Count As %
Agricultural and Biological Sciences 1 50%
Psychology 1 50%
Engineering 1 50%