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Computer Systems: Architectures, Modeling, and Simulation

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Cover of 'Computer Systems: Architectures, Modeling, and Simulation'

Table of Contents

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    Book Overview
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    Chapter 1 The Molen Programming Paradigm
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    Chapter 2 Loading ρμ -Code: Design Considerations
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    Chapter 3 RAMPASS: Reconfigurable and Advanced Multi-processing Architecture for Future Silicon Systems
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    Chapter 4 Basic OS Support for Distributed Reconfigurable Hardware
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    Chapter 5 A Cost-Efficient RISC Processor Platform for Real Time Audio Applications
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    Chapter 6 Customising Processors: Design-Time and Run-Time Opportunities
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    Chapter 7 Intermediate Level Components for Reconfigurable Platforms
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    Chapter 8 Performance Estimation of Streaming Media Applications for Reconfigurable Platforms
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    Chapter 9 CoDeL: Automatically Synthesizing Network Interface Controllers
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    Chapter 10 Performance and Power Evaluation of Clustered VLIW Processors with Wide Functional Units
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    Chapter 11 An Optimized Flow for Designing High-Speed, Large-Scale CMOS ASIC SoCs
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    Chapter 12 Register-Based Permutation Networks for Stride Permutations
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    Chapter 13 A Family of Accelerators for Matrix-Vector Arithmetics Based on High-Radix Multiplier Structures
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    Chapter 14 Metrics for Digital Signal Processing Architectures Characterization: Remanence and Scalability
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    Chapter 15 Virtual Architecture Mapping: A SystemC Based Methodology for Architectural Exploration of System-on-Chip Designs
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    Chapter 16 Comparison of Data Dependence Analysis Tests
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    Chapter 17 MOUSE: A Shortcut from Matlab Source to SIMD DSP Assembly Code
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    Chapter 18 High-Level Energy Estimation for ARM-Based SOCs
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    Chapter 19 IDF Models for Trace Transformations: A Case Study in Computational Refinement
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    Chapter 20 Programming Extremely Flexible Platforms
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    Chapter 21 The Virtex II Pro TM MOLEN Processor
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    Chapter 22 Reconfigurable Hardware for a Scalable Wavelet Video Decoder and Its Performance Requirements
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    Chapter 23 Design Space Exploration for Configurable Architectures and the Role of Modeling, High-Level Program Analysis and Learning Techniques
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    Chapter 24 Modeling Loop Unrolling: Approaches and Open Issues
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    Chapter 25 Self-loop Pipelining and Reconfigurable Dataflow Arrays
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    Chapter 26 Architecture Exploration for 3G Telephony Applications Using a Hardware–Software Prototyping Platform
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    Chapter 27 Embedded Context Aware Hardware Component Generation for Dataflow System Exploration
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    Chapter 28 On the (Re-)Use of IP-Components in Re-configurable Platforms
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    Chapter 29 Customising Hardware Designs for Elliptic Curve Cryptography
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    Chapter 30 Dynamic Hardware Reconfigurations: Performance Impact for MPEG2
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    Chapter 31 Compiler and System Techniques for s o c Distributed Reconfigurable Accelerators
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    Chapter 32 Design Space Exploration with Automatic Selection of SW and HW for Embedded Applications
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    Chapter 33 On Enhancing SIMD-Controlled DSPs for Performing Recursive Filtering
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    Chapter 34 Memory Bandwidth Requirements of Tile-Based Rendering
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    Chapter 35 Using CoDeL to Rapidly Prototype Network Processsor Extensions
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    Chapter 36 Synchronous Transfer Architecture (STA)
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    Chapter 37 Generated DSP Cores for Implementation of an OFDM Communication System
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    Chapter 38 A Novel Data-Path for Accelerating DSP Kernels
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    Chapter 39 Scalable FFT Processors and Pipelined Butterfly Units
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    Chapter 40 Scalable Instruction-Level Parallelism
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    Chapter 41 A Low-Power Multithreaded Processor for Baseband Communication Systems
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    Chapter 42 Initial Evaluation of Multimedia Extensions on VLIW Architectures
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    Chapter 43 HIBI v.2 Communication Network for System-on-Chip
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    Chapter 44 DIF: An Interchange Format for Dataflow-Based Design Tools
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    Chapter 45 Scalable and Modular Scheduling
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    Chapter 46 Early ISS Integration into Network-on-Chip Designs
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    Chapter 47 Cycle Accurate Simulation Model Generation for SoC Prototyping
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    Chapter 48 Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting
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    Chapter 49 A Communication-Centric Design Flow for HIBI-Based SoCs
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    Chapter 50 Performance Analysis of SoC Communication by Application of Deterministic and Stochastic Petri Nets
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    Chapter 51 Communication Optimization in Compaan Process Networks
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    Chapter 52 Analysis of Dataflow Programs with Interval-Limited Data-Rates
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    Chapter 53 High-Speed Event-Driven RTL Compiled Simulation
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    Chapter 54 A High-Level Programming Paradigm for SystemC
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    Chapter 55 Power, Performance and Area Exploration for Data Memory Assignment of Multimedia Applications
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    Chapter 56 Constraints Derivation and Propagation for Large-Scale Embedded Systems Exploration
Attention for Chapter 30: Dynamic Hardware Reconfigurations: Performance Impact for MPEG2
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Chapter title
Dynamic Hardware Reconfigurations: Performance Impact for MPEG2
Chapter number 30
Book title
Computer Systems: Architectures, Modeling, and Simulation
Published by
Springer, Berlin, Heidelberg, July 2004
DOI 10.1007/978-3-540-27776-7_30
Book ISBNs
978-3-54-022377-1, 978-3-54-027776-7
Authors

Elena Moscu Panainte, Koen Bertels, Stamatis Vassiliadis

Mendeley readers

Mendeley readers

The data shown below were compiled from readership statistics for 2 Mendeley readers of this research output. Click here to see the associated Mendeley record.

Geographical breakdown

Country Count As %
Unknown 2 100%

Demographic breakdown

Readers by professional status Count As %
Student > Ph. D. Student 1 50%
Professor > Associate Professor 1 50%
Readers by discipline Count As %
Computer Science 1 50%
Engineering 1 50%