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Chapter title |
Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) Using Path-Based Static Timing Analysis (STA) Technique
|
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Chapter number | 23 |
Book title |
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
|
Published by |
Springer, Berlin, Heidelberg, September 2006
|
DOI | 10.1007/11847083_23 |
Book ISBNs |
978-3-54-039094-7, 978-3-54-039097-8
|
Authors |
B. Chung, J. B. Kuo, Chung, B., Kuo, J. B. |