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Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation

Overview of attention for book
Cover of 'Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation'

Table of Contents

  1. Altmetric Badge
    Book Overview
  2. Altmetric Badge
    Chapter 1 Design of Parallel Implementations by Means of Abstract Dynamic Critical Path Based Profiling of Complex Sequential Algorithms
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    Chapter 2 Software Simultaneous Multi-Threading, a Technique to Exploit Task-Level Parallelism to Improve Instruction- and Data-Level Parallelism
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    Chapter 3 Handheld System Energy Reduction by OS-Driven Refresh
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    Chapter 4 Delay Constrained Register Transfer Level Dynamic Power Estimation
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    Chapter 5 Circuit Design Style for Energy Efficiency: LSDL and Compound Domino
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    Chapter 6 Accurate PTV, State, and ABB Aware RTL Blackbox Modeling of Subthreshold, Gate, and PN-Junction Leakage
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    Chapter 7 Leakage Power Characterization Considering Process Variations
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    Chapter 8 Heuristic for Two-Level Cache Hierarchy Exploration Considering Energy Consumption and Performance
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    Chapter 9 System Level Multi-bank Main Memory Configuration for Energy Reduction
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    Chapter 10 SRAM CP: A Charge Recycling Design Schema for SRAM
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    Chapter 11 Compiler-Driven Leakage Energy Reduction in Banked Register Files
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    Chapter 12 Impact of Array Data Flow Analysis on the Design of Energy-Efficient Circuits
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    Chapter 13 Methodology for Energy-Efficient Digital Circuit Sizing: Important Issues and Design Limitations
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    Chapter 14 Low-Power Adaptive Bias Amplifier for a Large Supply-Range Linear Voltage Regulator
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    Chapter 15 Circuit Sizing and Supply-Voltage Selection for Low-Power Digital Circuit Design
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    Chapter 16 Power Modeling of a NoC Based Design for High Speed Telecommunication Systems
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    Chapter 17 Partial Bus-Invert Bus Encoding Schemes for Low-Power DSP Systems Considering Inter-wire Capacitance
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    Chapter 18 Estimation of Power Reduction by On-Chip Transmission Line for 45nm Technology
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    Chapter 19 Two Efficient Synchronous $\Leftrightarrow$ Asynchronous Converters Well-Suited for Network on Chip in GALS Architectures
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    Chapter 20 Low-Power Maximum Magnitude Computation for PAPR Reduction in OFDM Transmitters
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    Chapter 21 Dynamic Management of Thermally-Induced Clock Skew: An Implementation Perspective
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    Chapter 22 A Clock Generator Driven by a Unified-CBiCMOS Buffer Driver for High Speed and Low Energy Operation
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    Chapter 23 Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) Using Path-Based Static Timing Analysis (STA) Technique
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    Chapter 24 Low Power Distance Measurement Unit for Real-Time Hardware Motion Estimators
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    Chapter 25 Reducing Energy Dissipation of Wireless Sensor Processors Using Silent-Store-Filtering MoteCache
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    Chapter 26 A Comparison of Two Approaches Providing Data Encryption and Authentication on a Processor Memory Bus
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    Chapter 27 Methodology for Dynamic Power Verification of Contactless Smartcards
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    Chapter 28 New Battery Status Checking Method for Implantable Biomedical Applications
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    Chapter 29 Considering Zero-Arrival Time and Block-Arrival Time in Hierarchical Functional Timing Analysis
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    Chapter 30 A Simple MOSFET Parasitic Capacitance Model and Its Application to Repeater Insertion Technique
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    Chapter 31 Zephyr: A Static Timing Analyzer Integrated in a Trans-hierarchical Refinement Design Flow
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    Chapter 32 Receiver Modeling for Static Functional Crosstalk Analysis
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    Chapter 33 Modeling of Crosstalk Fault in Defective Interconnects
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    Chapter 34 Body Bias Generator for Leakage Power Reduction of Low-Voltage Digital Logic Circuits
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    Chapter 35 Energy-Delay Space Analysis for Clocked Storage Elements Under Process Variations
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    Chapter 36 IR-drop Reduction Through Combinational Circuit Partitioning
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    Chapter 37 Low-Power Register File Based on Adiabatic Logic Circuits
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    Chapter 38 High Performance CMOS Circuit by Using Charge Recycling Active Body-Bias Controlled SOI
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    Chapter 39 Designing Alternative FPGA Implementations Using Spatial Data from Hardware Resources
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    Chapter 40 An FPGA Power Aware Design Flow
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    Chapter 41 Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
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    Chapter 42 Optimization of Master-Slave Flip-Flops for High-Performance Applications
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    Chapter 43 Hierarchical Modeling of a Fractional Phase Locked Loop
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    Chapter 44 Low Power and Low Jitter Wideband Clock Synthesizers in CMOS ASICs
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    Chapter 45 Statistical Characterization of Library Timing Performance
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    Chapter 46 Exploiting Narrow Values for Energy Efficiency in the Register Files of Superscalar Microprocessors
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    Chapter 47 Low Clock Swing D Flip-Flops Design by Using Output Control and MTCMOS
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    Chapter 48 Sensitivity of a Power Supply Damping Method to Resistance and Current Waveform Variations
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    Chapter 49 Worst Case Crosstalk Noise Effect Analysis in DSM Circuits by ABCD Modeling
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    Chapter 50 A Technique to Reduce Static and Dynamic Power of Functional Units in High-Performance Processors
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    Chapter 51 Correct Modelling of Nested Miller Compensated Amplifier for Discrete-Time Applications
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    Chapter 52 Spectral Analysis of the On-Chip Waveforms to Generate Guidelines for EMC-Aware Design
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    Chapter 53 A Scalable Power Modeling Approach for Embedded Memory Using LIB Format
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    Chapter 54 Improving Energy Efficiency Via Speculative Multithreading on MultiCore Processors
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    Chapter 55 A CMOS Compatible Charge Recovery Logic Family for Low Supply Voltages
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    Chapter 56 A Framework for Estimating Peak Power in Gate-Level Circuits
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    Chapter 57 QDI Latches Characteristics and Asynchronous Linear-Pipeline Performance Analysis
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    Chapter 58 Power Modeling of Precharged Address Bus and Application to Multi-bit DPA Attacks to DES Algorithm
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    Chapter 59 Adaptive Coding in Networks-on-Chip: Transition Activity Reduction Versus Power Overhead of the Codec Circuitry
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    Chapter 60 A Novel Methodology to Reduce Leakage Power in CMOS Complementary Circuits
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    Chapter 61 Techniques to Enhance the Resistance of Precharged Busses to Differential Power Analysis
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    Chapter 62 Formal Evaluation of the Robustness of Dual-Rail Logic Against DPA Attacks
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    Chapter 63 A Method for Switching Activity Analysis of VHDL-RTL Combinatorial Circuits
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    Chapter 64 Nanoelectronics: Challenges and Opportunities
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    Chapter 65 Static and Dynamic Power Reduction by Architecture Selection
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    Chapter 66 Asynchronous Design for High-Speed and Low-Power Circuits
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    Chapter 67 Design for Volume Manufacturing in the Deep Submicron ERA
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    Chapter 68 The Holy Grail of Holistic Low-Power Design
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    Chapter 69 Top Verification of Low Power System with “Checkerboard” Approach
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    Chapter 70 The Power Forward Initiative
Attention for Chapter 18: Estimation of Power Reduction by On-Chip Transmission Line for 45nm Technology
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Chapter title
Estimation of Power Reduction by On-Chip Transmission Line for 45nm Technology
Chapter number 18
Book title
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Published by
Springer, Berlin, Heidelberg, September 2006
DOI 10.1007/11847083_18
Book ISBNs
978-3-54-039094-7, 978-3-54-039097-8
Authors

Kenichi Okada, Takumi Uezono, Kazuya Masu