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Heuristic for Two-Level Cache Hierarchy Exploration Considering Energy Consumption and Performance
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Springer, Berlin, Heidelberg, September 2006
A. G. Silva-Filho, F. R. Cordeiro, R. E. Sant’Anna, M. E. Lima
The data shown below were compiled from readership statistics for 1 Mendeley reader of this research output. Click here to see the associated Mendeley record.
|Readers by professional status||Count||As %|
|Student > Master||1||100%|
|Readers by discipline||Count||As %|